[journal]
/ 1996
/ Altera Corporation
[journal]
/ 1996
/ Altera Corporation
[journal]
/ 1996
/ Advanced Micro Devices
[journal]
/ An `Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs” IEEE Transactions on Computer-Aided Design of Integrated Circuit and Systems
13
: 1~11
[journal]
/ “chortle-crf
/ Fast Technology Mapping for Lookup Table -Based FPGAs”
/ June 1991
: 227~233
[journal]
/ “Technology Mapping of Lookup Table-Based FPGAs for Performance” 1991 IEEE Conference on Computer Aided Design
: 568~571
[journal]
/ 1992
/ A system for sequential Circuit Synthesis“ Department of Electrical Engineering and Computer Science University of California
[journal]
/ 1998
/ “Technology Mapping for Large Complex PLDs”
: 698~703
[journal]
/ 1999
/ “시간적 조건에서 실행 시간을 개선한 CPLD 기술 매핑 알고리즘 개발”
4
(3)
: 35~46
[journal]
/ 2001
/ “A New Technology Mapping for CPLD under the time constraint” ASP-DAC
: 235~238
[journal]
/ 2005
/ 이관형. “상관관계에 의한 CLB구조의 CPLD 저전력 기술 매핑 알고리즘”
10
(2)
: 49~58