An Efficient CPLD Technology Mapping considering Area and the Time Constraint

Jaejin Kim; Kwan Hyeong, Lee

Journal of The Korea Society of Computer and Information

Abbr : JKSCI
2005, 10(3), pp.11-18
Publisher : The Korean Society Of Computer And Information
Research Area : Computer Science

Jaejin Kim ¹ , Kwan Hyeong, Lee ²

¹ 강동대학교
² 대진대학교

ABSTRACT

In this paper, we propose a new technology mapping algorithm for CPLD consider area under time constraint. This algorithm detect feedbacks from boolean networks, then variables that have feedback are replaced to temporary variables. Creating the temporary variables transform sequential circuit to combinational circuit. The transformed circuits are represented to DAG. After traversing all nodes in DAG, the nodes that have output edges more than two are replicated and reconstructed to fanout free tree. Using time constraints and delay time of device, the number of graph partitionable multi-level is decided. Several nodes in partitioned clusters are merged by collapsing, and are fitted to the number of OR-terms in a given CLB by bin packing.Proposed algorithm have been applied to MCNC logic synthesis benchmark circuits, and have reduced the number of CLBs by 62.2% than those of DDMAP. And reduced the number of CLBs by 17.6% than those of TEMPLA.
KEYWORDS

CPLD , Technology Mapping
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