A RTL Binding Technique and Low Power Technology Mapping consider CPLD

Jaejin Kim; Kwan Hyeong, Lee

KJC Korea
Journal Central

Journal of The Korea Society of Computer and Information

Korean | English

pISSN : 1598-849X / eISSN : 2383-9945

2020 KCI Impact Factor : 0.4

BACK
TOP

Home > Explore Content > All Issues > Article View

1 of 36

A RTL Binding Technique and Low Power Technology Mapping consider CPLD

Journal of The Korea Society of Computer and Information

Abbr : JKSCI
2006, 11(2), pp.1-6
Publisher : The Korean Society Of Computer And Information
Research Area : Computer Science

Jaejin Kim ¹ , Kwan Hyeong, Lee ²

¹ 강동대학교
² 대진대학교

ABSTRACT

In this paper, a RTL binding technique and low power technology mapping consider CPLD is proposed. Allocation processing selected module consider the module calculation after scheduling process for circuit by HDL. Select CPLD for constrain after allocation. A Boolean equation is partitioned for CLB by allocated modules. The proposed binding algorithm is description using optimum CLB within a CPLD consider low power. The proposed algorithm is examined by using 16 bit FIR filter. In the case that applicate the algorithm, the experiments results show reduction in the power consumption by 43% comparing with that of non application algorithm.攀제1저자 : 김재진교신저자 : 이관형접수일 : 2006.2.3, 심사완료일 : 2006.5.18*극동정보대학 컴퓨터정보과 교수, **청주대학교 전자정보공학부 전임강사攀攀
KEYWORDS
REFERENCES (8)

[journal] / 1992 / Accurate Layout Area and Delay Modeling for System Level Design (v)

[journal] / Aug.1995 / Chip Level Area and Timing Estimation for Lookup Table Based FPGAs

[journal] / 1992 / “Benchmarks for the 1992 High Level Synthesis Workshop”

[journal] / 1994 / An Algorithm for solving The Binding Problem” 7th International Conference on VLSI Design : 163~168

[journal] / 1999 / “시간적 조건에서 실행 시간을 개선한 CPLD 기술 매핑 알고리즘 개발” 4 (3) : 35~46

[journal] / January2001 / A New Technology Mapping for CPLD under the time constraint : 235~238

[journal] / 2005 / “상관관계에 위한 CLB 구조의 CPLD 저전력 기술 매핑 알고리즘” 10 (2) : 49~57

[journal] / 2005 / “시간제약 조건과 면적을 고려한 효율적인 CPLD 기술 매핑” 10 (3) : 11~18
KCI Citation (0)

KJC Korea
Journal Central

Statistics

Tools