A RTL Binding Technique and Low Power Technology Mapping consider CPLD

KJC Korea
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pISSN : 1598-849X / eISSN : 2383-9945

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A RTL Binding Technique and Low Power Technology Mapping consider CPLD

¹강동대학교
²대진대학교

ABSTRACT
열림/닫힘 버튼

In this paper, a RTL binding technique and low power technology mapping consider CPLD is proposed. Allocation processing selected module consider the module calculation after scheduling process for circuit by HDL. Select CPLD for constrain after allocation. A Boolean equation is partitioned for CLB by allocated modules. The proposed binding algorithm is description using optimum CLB within a CPLD consider low power. The proposed algorithm is examined by using 16 bit FIR filter. In the case that applicate the algorithm, the experiments results show reduction in the power consumption by 43% comparing with that of non application algorithm.攀제1저자 : 김재진교신저자 : 이관형접수일 : 2006.2.3, 심사완료일 : 2006.5.18*극동정보대학 컴퓨터정보과 교수, **청주대학교 전자정보공학부 전임강사攀攀
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열림/닫힘 버튼

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