[journal]
/ 1995
/ “A Survey of Optimization Techniques Targeting Low Power VLSI Circuits”
: 242~247
[journal]
/ 1992
/ “Testability measures in pseudorandom testing”
: 794~800
[journal]
/ An `Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs” IEEE Transactions on Computer-Aided Design of Integrated Circuit and Systems
: 1~11
[journal]
/ Fast Technology Mapping for Lookup Table-Based FPGAs”
: 227~233
[journal]
/ 2001
/ “Power Minimization in LUT-Based FPGA Technology Mapping”
: 635~640
[journal]
/ 1994
/ “FPGA Technology Mapping for Power Minimization” Workshop on field Programmable Logic and Applications
: 66~77
[journal]
/ 1997
/ apping by Hiding high-Transition Paths in Invisible Edges of LUT-Based FPGAs”
: 1536~1539
[journal]
/ “Technology Mapping of Lookup Table-Based FPGAs for Performance” 1991 IEEE Conference on Computer Aided Design
: 568~571
[journal]
/ 1992
/ A system for sequential Circuit Synthesis” Department of Electrical Engineering and Computer Science University of California
[journal]
/ 1998
/ “Technology Mapping for Large Complex PLDs”
: 698~703
[journal]
/ 1999
/ “시간적 조건에서 실행 시간을 개선한 CPLD 기술 매핑 알고리즘 개발”
4(3)
: 35~46
[journal]
/ 2001
/ “A New Technology Mapping for CPLD under the time constraint” ASP-DAC
: 235~238
[journal]
/ 2003
/ Liquid Crystal On Silicon 를 위한 컬러 콘트롤 드라이브 설계”
/ 한국컴퓨터정보학회 vol 8권 2호
8(2)
: 57~63