Deep packet inspection which perform pattern matching to search for malicious patterns in the packet is most computationally intensive task. Hardware-based pattern matching is required for real-time packet inspection in high-speed network. In this paper, we have designed and implemented network intrusion detection hardware as a Microblaze-based SoC using Virtex-6 FPGA, which capture the network input packet, perform hardware-based pattern matching for patterns in the Snort rule, and provide the matching result to the software. We verify the operation of the implemented system using traffic generator and real network traffic. The implemented hardware can be used in network intrusion detection system operated in wire-speed.
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@article{ART001654944}, author={김택훈 and SangKyun Yun}, title={The Design and Implementation of Network Intrusion Detection System Hardware on FPGA}, journal={Journal of The Korea Society of Computer and Information}, issn={1598-849X}, year={2012}, volume={17}, number={4}, pages={11-18}, doi={}
TY - JOUR AU - 김택훈 AU - SangKyun Yun TI - The Design and Implementation of Network Intrusion Detection System Hardware on FPGA JO - Journal of The Korea Society of Computer and Information PY - 2012 VL - 17 IS - 4 PB - The Korean Society Of Computer And Information SP - 11 EP - 18 SN - 1598-849X AB - Deep packet inspection which perform pattern matching to search for malicious patterns in the packet is most computationally intensive task. Hardware-based pattern matching is required for real-time packet inspection in high-speed network. In this paper, we have designed and implemented network intrusion detection hardware as a Microblaze-based SoC using Virtex-6 FPGA, which capture the network input packet, perform hardware-based pattern matching for patterns in the Snort rule, and provide the matching result to the software. We verify the operation of the implemented system using traffic generator and real network traffic. The implemented hardware can be used in network intrusion detection system operated in wire-speed. KW - Instrusion Detection;FPGA;Pattern Matching Hardware DO - ER -
김택훈 and SangKyun Yun. (2012). The Design and Implementation of Network Intrusion Detection System Hardware on FPGA. Journal of The Korea Society of Computer and Information, 17(4), 11-18.
김택훈 and SangKyun Yun. 2012, "The Design and Implementation of Network Intrusion Detection System Hardware on FPGA", Journal of The Korea Society of Computer and Information, vol.17, no.4 pp.11-18. Available from: doi:
김택훈, SangKyun Yun "The Design and Implementation of Network Intrusion Detection System Hardware on FPGA" Journal of The Korea Society of Computer and Information 17.4 pp.11-18 (2012) : 11.
김택훈, SangKyun Yun. The Design and Implementation of Network Intrusion Detection System Hardware on FPGA. 2012; 17(4), 11-18. Available from: doi:
김택훈 and SangKyun Yun. "The Design and Implementation of Network Intrusion Detection System Hardware on FPGA" Journal of The Korea Society of Computer and Information 17, no.4 (2012) : 11-18.doi:
김택훈; SangKyun Yun. The Design and Implementation of Network Intrusion Detection System Hardware on FPGA. Journal of The Korea Society of Computer and Information, 17(4), 11-18. doi:
김택훈; SangKyun Yun. The Design and Implementation of Network Intrusion Detection System Hardware on FPGA. Journal of The Korea Society of Computer and Information. 2012; 17(4) 11-18. doi:
김택훈, SangKyun Yun. The Design and Implementation of Network Intrusion Detection System Hardware on FPGA. 2012; 17(4), 11-18. Available from: doi:
김택훈 and SangKyun Yun. "The Design and Implementation of Network Intrusion Detection System Hardware on FPGA" Journal of The Korea Society of Computer and Information 17, no.4 (2012) : 11-18.doi: