Home > Explore Content > All Issues > Article View
Parallel Branch Instruction Extension for Thumb-2 Instruction Set Architecture
Journal of The Korea Society of Computer and Information
Abbr :
JKSCI
2013, 18(7), pp.1-10
Publisher : The Korean Society Of Computer And Information
Research Area : Computer Science
2013, 18(7), pp.1-10
Publisher : The Korean Society Of Computer And Information
Research Area : Computer Science
-
In this paper, the parallel branch instruction is proposed which executes a branch instruction and the frequently used instruction simultaneously to improve the performance of Thumb-2instruction set architecture. In the proposed approach, new 32-bit parallel branch instructions are introduced which combine 16-bit branch instruction with each of the frequently used 16-bit LOAD,ADD, MOV, STORE, and SUB instructions, respectively. To provide the encoding space of the new instructions, the register field in less frequently executed instructions is reduced, and the new instructions are encoded by using the saved bits. Experiments show that the proposed approach improves performance by an average of 8.0% when compared to the conventional approach.
162 Viewed
Print this page
Download PDF