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Analysis on the Temperature of Multi-core Processors according to Placement of Functional Units and L2 Cache
Journal of The Korea Society of Computer and Information
Abbr :
JKSCI
2014, 19(4), pp.1-8
Publisher : The Korean Society Of Computer And Information
Research Area : Computer Science
2014, 19(4), pp.1-8
Publisher : The Korean Society Of Computer And Information
Research Area : Computer Science
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As cores in multi-core processors are integrated in a single chip, power density increasedconsiderably, resulting in high temperature. For this reason, many research groups have focused on the techniques to solve thermal problems. In general, the approaches using mechanical coolingsystem or DTM(Dynamic Thermal Management) have been used to reduce the temperature in themicroprocessors. However, existing approaches cannot solve thermal problems due to high cost andperformance degradation. However, floorplan scheme does not require extra cooling cost andperformance degradation. In this paper, we propose the diverse floorplan schemes in order toalleviate the thermal problem caused by the hottest unit in multi-core processors. Simulationresults show that the peak temperature can be reduced efficiently when the hottest unit is locatednear to L2 cache. Compared to baseline floorplan, the peak temperature of core-central andcore-edge are decreased by 8.04℃, 8.05℃ on average, respectively.
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