[confproc]
A. Sodani
/ 2011
/ Race to Exascale: Opportunities and Challenges
/ MICRO 2011 Keynote
[web]
/ 2013
/ NVIDIA Tegra 4 Family CPU Architecture, NVIDIA, Tech. Rep.
/ http://www.nvidia.com/docs/IO/116757/NVIDIA_Quad_a15_whitepaper_FINALv2.pdf
[confproc]
A. Sembrant
/ 2013
/ TLC : A Tag Less Cache for Reducing Dynamic First Level Cache Energy
/ Proc. of IEEE/ACM International Symposium on Microarchitecture
: 49~61
[confproc]
M. D. Powell
/ 2001
/ Reducing Set-associative Cache Energy via Way-Prediction and Selective Direct-mapping
/ MICRO
: 54~65
[confproc]
W. Zhang
/ 2015
/ Reducing Dynamic Energy of Set-associative L1 Instruction Cache by Early Tag Lookup
/ Low Power Electronics and Design
: 49~54
[journal]
J. Dai
/ 2014
/ Exploiting Early Tag Access for Reducing L1 data cache energy in embedded processors
/ IEEE Transactions on Very Large Scale Integration Systems
22
(2)
: 396~407
[journal]
C. Zhang
/ 2005
/ A Way-Halting Cache for Low-Energy High-Performance Systems
/ ACM Transactions on Architecture and Code optimization
2
(1)
: 34~54
[journal]
J. Dai
/ 2013
/ An Energy-Efficient L2 Cache Architecture using Way Tag Information under Write-through Policy
/ IEEE Transactions on Very Large Scale Integration Systems
21
(1)
: 102~112
[confproc]
D. Sanchez
/ 2010
/ The ZCache : Decoupling Ways and Associativity
/ Microarchitecture
(1)
: 187~198
[journal]
André Seznec
/ 1993
/ A case for two-way skewed-associative caches
/ ACM SIGARCH Computer Architecture News
/ Association for Computing Machinery (ACM)
21
(2)
: 169~178
/ https://doi.org/10.1145/173682.165152
[book]
A. Seznec
/ 1993
/ Skewed-Associative Caches
: 305~316
[confproc]
C. L Yang
/ 2004
/ Hotspot Cache: Joint Temporal and Spatial Locality Exploitation for I-cache Energy Reduction
/ Low Power Electronics and Design
: 114~111
[journal]
J. Ye
/ 2012
/ A Behavior-based Adaptive Access-Mode for Low-Power Set-Associative Caches in Embedded systems
/ Jornal of Information processing
20
(1)
: 26~36
[journal]
A. ma
/ 2001
/ Way Memorization to Reduce Fetch Energy in Instruction Caches
/ ISCA Workshop on Complexity Effective Design
20
: 31~
[journal]
C. H. Kim
/ 2005
/ A Power-aware Branch Predictor by Accessing BTB Selectively
/ Jornal of Computer Science and Technology
20
(5)
: 607~614
[journal]
T. Austin
/ 2002
/ SimpleScalar : An Infrastructure for Computer System Modeling
/ Computer
35
(2)
: 59~67
[web]
/ Wattch
/ http://www.eecs.harvard.edu/~dbrooks/
[web]
/ SPEC Benchmark Suite
/ http://spec.org/cpu2006/
[web]
/ SPEC CPU2000 Benchmarks
/ http://www.specbench.org
[report]
N. Muralimanohar
/ 2009
/ CACTI 6.0: A Tool to Model Large Caches
/ Hewlett Packard Laboratories