[web]
JEDEC Solid State Technology Association
/ 2014
/ Lower Double Data Rate 4 (LPDDR4)
/ https://www.jedec.org
[web]
JEDEC Solid State Technology Association
/ 2013
/ High Bandwidth Memory (HBM)
/ https://www.jedec.org
[confproc]
K. Lim
/ 2008
/ Understanding and designing new server architectures for emerging warehouse-computing environments
/ Proceedings of the 35th Annual International Symposium on Computer Architecture (ISCA)
: 315~326
[confproc]
D. Meisner
/ 2009
/ PowerNap:Eliminating server idle power
/ Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS XIV)
: 205~216
[confproc]
Y. Lee
/ 2013
/ Skinflint DRAM System:Minimizing DRAM Chip Writes for Low Power
/ Proceedings of the 19th International Symposium on High Performance Computer Architecture (HPCA)
: 25~34
[confproc]
J. Ahn
/ 2009
/ Future Scaling of Processor-memory Interfaces
/ Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis (SC)
: 1~12
[confproc]
A. N. Udipi
/ 2010
/ Rethinking DRAM Design and Organization for Energy-constrained Multi-cores
/ Proceedings of the 37th annual International Symposium on Computer Architecture (ISCA)
: 175~186
[confproc]
H. Zheng
/ 2008
/ Mini-rank: Adaptive DRAM Architecture for Improving Memory Power Efficiency
/ Proceedings of the 41st IEEE/ACM International Symposium on Microarchitecture (MICRO)
: 210~221
[confproc]
D. Shin
/ 2012
/ Adaptive Page Grouping for Energy Efficiency in Hybrid PRAM-DRAM Main Memory
/ Proceedings of the 2012 ACM Research in Applied Computation Symposium
: 395~402
[confproc]
Thaleia Dimitra Doudali
/ 2019
/ Kleio : A Hybrid Memory Page Scheduler with Machine Intelligence
/ Proceedings of the 28th International Symposium on High-Performance Parallel and Distributed Computing (HPDC)
: 37~48
[confproc]
L. Ramos
/ 2011
/ Page Placement in Hybrid Memory Systems
/ Proceedings of the International Conference on Supercomputing (ICS)
: 85~95
[journal]
Ilhoon Shin
/ 2011
/ Hot/cold clustering for page mapping in NAND flash memory
/ IEEE Transactions on Consumer Electronics
/ Institute of Electrical and Electronics Engineers (IEEE)
57
(4)
: 1728~1731
/ 10.1109/TCE.2011.6131147
[book]
S. W. Ng
/ 2007
/ Memory Systems: Cache, DRAM, Disk
/ Morgan Kaufmann Publishers
[confproc]
Z. Zhang
/ 2000
/ A Permutation-based Page Interleaving Scheme to Reduce Row-buffer Conflicts and Exploit Data Locality
/ Proceedings of the 33rd IEEE/ACM International Symposium on Microarchitecture (MICRO)
: 32~41
[journal]
N. Binkert
/ 2011
/ The Gem5 Simulator
/ SIGARCH Computer Architecture News
39
(2)
[other]
R. Balasubramonian
/ 2009
/ CACTI 6.0: A Tool to Model Large Caches
/ HP Laboratories
[web]
J. L. Henning
/ 2006
/ SPEC CPU2006 Benchmark Descriptions
/ ACM SIGARCH Computer Architecture News
/ https://www.spec.org
[confproc]
K. Ning
/ 2004
/ Bus Power Estimation and Power-Efficient Bus Arbitration for System-on-a-Chip Embedded Systems
/ Proceedings of the 4th International Conference on Power-Aware Computer Systems (PACS)
: 95~106
[journal]
Dake Liu
/ 1994
/ Power consumption estimation in CMOS VLSI chips
/ IEEE Journal of Solid-State Circuits
/ Institute of Electrical and Electronics Engineers (IEEE)
29
(6)
: 663~670
/ 10.1109/4.293111