A Design and Implementation of Cryptographic Processor DNAES Flexibly Internet of Things Network
2017, 12(4), pp.591-597
DOI : 10.34163/jkits.2017.12.4.013
Publisher : Korea Knowledge Information Technology Society
Research Area : Interdisciplinary Research
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With the rapid development of the Internet environment, the importance of security for terminals of wireless networks is increasing. In the case of a sensor node, which is often used as a wireless network terminal in the Internet environment, a resource environment such as a memory is poor. Therefore, there is a problem that a memory-intensive security algorithm can not be used. In this paper, we propose the DNAES algorithm considering the security problem when the number of sensors increases because it enables the poor resource environment, low power and high speed processing of sensor nodes. The proposed DNAES encryption algorithm adopts the DN-R technique which reduces the load of important nodes in the wireless network environment. Implementation of the DNAES encryption algorithm was performed using topology of verilog-HDL. The tool used for circuit synthesis was Synopsys Design Analyzer and QUARTUS 12.0. The tools used in the simulation were Synopsys VHDL Debugger, ModelSim 5.8C. Simulation results show that the proposed DNAES encryption algorithm has a 120% increase in throughput compared to the conventional AES algorithm. Therefore, it is considered that the DNAES proposed in this paper is sufficient for the security of the sensor node in the IOT environment.
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