A Filtering Scheme to Improve the Performance of Last Level Cache

Youngil Cho

doi:10.34163/jkits.2017.12.5.001

The last level cache(LLC) is commonly managed using LRU policy. However, LRU has a high overhead cost of moving cache lines into the most recently used position whenever a cache line is accessed. Also, LRU is prone to cache pollution when a sequence of single-use memory accesses that are larger than the cache size is fetched from memory. Cache performance and efficiency can be improved if some subset of these reuse lines can reside in the cache longer. Previous schemes approach this by bypassing never reused lines(0-reused lines). But, sometimes they deliver no benefit due to the lack of never reused lines. This paper proposes a new mechanism that filters out not only 0-reused lines but also 1-reused lines and accurately predicts 0/1-reused lines from incoming lines. Filtering of 0/1-reused lines provides more opportunities to fit the working set into cache size. Our proposed scheme is evaluated using a simulation environment where its effectiveness and performance-improvement capabilities are demonstrated. We present experimental results showing miss rate and IPC(Instruction Per Cycle) comparison of the proposed scheme and OBM(Optimal Bypass Monitor) against LRU for SPEC CPU2006 benchmarks. The result shows that the proposed scheme and OBM can improve IPC by an average of 20.1% and 14.4%, respectively. And the proposed scheme reduces the miss rate by 20.6% compared to LRU.

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* 2022년 이후 발행 논문의 참고문헌은 현재 구축 중입니다.

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