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Power-Delay Product Optimization of Heterogeneous Adder Using Integer Linear Programming

  • Journal of The Korea Society of Computer and Information
  • Abbr : JKSCI
  • 2010, 15(10), pp.1-9
  • Publisher : The Korean Society Of Computer And Information
  • Research Area : Engineering > Computer Science

곽상훈 1 이정근 2 Jeong-A Lee 3

1서울대학교
2한림대학교
3조선대학교

Accredited

ABSTRACT

In this paper, we propose a methodology in which a power-delay product of a binary adder is optimized based on the heterogeneous adder architecture. We formulate the power-delay product of the heterogeneous adder by using integer linear programming(ILP). For the use of ILP optimization, we adopt a transformation technique in which the initial non-linear expression for the power-delay product is converted into linear expression. The experimental result shows the superiority of the suggested method compared to the cases in which only conventional adder is used.

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