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Implementation and Verification of JPEG Decoder IP using a Virtual Platform

  • Journal of The Korea Society of Computer and Information
  • Abbr : JKSCI
  • 2011, 16(11), pp.1-8
  • Publisher : The Korean Society Of Computer And Information
  • Research Area : Engineering > Computer Science

정용범 1 김용민 1 황철희 1 김종면 1

1울산대학교

Accredited

ABSTRACT

The requirement of a system-on-a-chip (SoC) design is increasing, which combines various and complex functional units on a single device. However, short time to market prohibits to release the device. To satisfy this shorter time-to-market, verification of both hardware and software at the same time is important. A virtual platform-based design method supports faster verification of these combined software and hardware by reusing pre-defined intellectual properties (IP). In this paper, we introduce the virtual platform-based design and redesign the existing ARM processor based S3C2440A system using the virtual platform-based method. In addtion, we implement and evaluate the performance of a JPEG decoder on the S3C2440A virtual platform. Furthermore, we introduce an optimized technique of the JPEG decoder using the ARM based inline assembly language, and then verify the performance improvement on the virtual platform. Such virtual platform-based design allows to verify both software and hardware at the same time and can meet the requirement of the shorter time-to-market.

Citation status

* References for papers published after 2022 are currently being built.

This paper was written with support from the National Research Foundation of Korea.