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@article{ART001804458},
author={Jong Wook Kwak},
title={Low-Power Cache Design by using Locality Buffer and Address Compression},
journal={Journal of The Korea Society of Computer and Information},
issn={1598-849X},
year={2013},
volume={18},
number={9},
pages={11-19}

TY - JOUR
AU - Jong Wook Kwak
TI - Low-Power Cache Design by using Locality Buffer and Address Compression
JO - Journal of The Korea Society of Computer and Information
PY - 2013
VL - 18
IS - 9
PB - The Korean Society Of Computer And Information
SP - 11
EP - 19
SN - 1598-849X
AB - Most modern computer systems employ cache systems in order to alleviate the access time gap between processor and memory system. The power dissipated by the cache systems becomes a significant part of the total power dissipated by whole microprocessor chip. Therefore, power reduction in the cache system becomes one of the important issues. Partial tag cache is the system for the least power consumption. The main power reduction for this method is due to the use of small partial tag matching, not full tag matching. In this paper, we first analyze the previous regular partial tag cache systems and propose a new address matching mechanism by using locality buffer and address compression. In simulation results, the proposed model shows 18% power reduction in average, still providing same performance level, compared to regular cache.
KW - Low power cache;Partial tag cache;Locality;Cache tag;Address compression
DO -
UR -
ER -

Jong Wook Kwak. (2013). Low-Power Cache Design by using Locality Buffer and Address Compression. Journal of The Korea Society of Computer and Information, 18(9), 11-19.

Jong Wook Kwak. 2013, "Low-Power Cache Design by using Locality Buffer and Address Compression", Journal of The Korea Society of Computer and Information, vol.18, no.9 pp.11-19.

Jong Wook Kwak "Low-Power Cache Design by using Locality Buffer and Address Compression" Journal of The Korea Society of Computer and Information 18.9 pp.11-19 (2013) : 11.

Jong Wook Kwak. Low-Power Cache Design by using Locality Buffer and Address Compression. 2013; 18(9), 11-19.

Jong Wook Kwak. "Low-Power Cache Design by using Locality Buffer and Address Compression" Journal of The Korea Society of Computer and Information 18, no.9 (2013) : 11-19.

Jong Wook Kwak. Low-Power Cache Design by using Locality Buffer and Address Compression. Journal of The Korea Society of Computer and Information, 18(9), 11-19.

Jong Wook Kwak. Low-Power Cache Design by using Locality Buffer and Address Compression. Journal of The Korea Society of Computer and Information. 2013; 18(9) 11-19.

Jong Wook Kwak. Low-Power Cache Design by using Locality Buffer and Address Compression. 2013; 18(9), 11-19.

Jong Wook Kwak. "Low-Power Cache Design by using Locality Buffer and Address Compression" Journal of The Korea Society of Computer and Information 18, no.9 (2013) : 11-19.