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@article{ART002032855},
author={공준호},
title={Variable latency L1 data cache architecture design in multi-core processor under process variation},
journal={Journal of The Korea Society of Computer and Information},
issn={1598-849X},
year={2015},
volume={20},
number={9},
pages={1-10}

TY - JOUR
AU - 공준호
TI - Variable latency L1 data cache architecture design in multi-core processor under process variation
JO - Journal of The Korea Society of Computer and Information
PY - 2015
VL - 20
IS - 9
PB - The Korean Society Of Computer And Information
SP - 1
EP - 10
SN - 1598-849X
AB - In this paper, we propose a new variable latency L1 data cache architecture for multi-core processors. Our proposed architecture extends the traditional variable latency cache to be geared toward the multi-core processors. We added a specialized data structure for recording the latency of the L1 data cache. Depending on the added latency to the L1 data cache, the value stored to the data structure is determined. It also tracks the remaining cycles of the L1 data cache which notifies data arrival to the reservation station in the core. As in the variable latency cache of the single-core architecture, our proposed architecture flexibly extends the cache access cycles considering process variation. The proposed cache architecture can reduce yield losses incurred by L1 cache access time failures to nearly 0%. Moreover, we quantitatively evaluate performance, power, energy consumption, power-delay product, and energy-delay product when increasing the number of cache access cycles.
KW - Process variation;Variable latency cache architecture;Cache access time failure;Processor yield loss;Multi-core architecture
DO -
UR -
ER -

공준호. (2015). Variable latency L1 data cache architecture design in multi-core processor under process variation. Journal of The Korea Society of Computer and Information, 20(9), 1-10.

공준호. 2015, "Variable latency L1 data cache architecture design in multi-core processor under process variation", Journal of The Korea Society of Computer and Information, vol.20, no.9 pp.1-10.

공준호 "Variable latency L1 data cache architecture design in multi-core processor under process variation" Journal of The Korea Society of Computer and Information 20.9 pp.1-10 (2015) : 1.

공준호. Variable latency L1 data cache architecture design in multi-core processor under process variation. 2015; 20(9), 1-10.

공준호. "Variable latency L1 data cache architecture design in multi-core processor under process variation" Journal of The Korea Society of Computer and Information 20, no.9 (2015) : 1-10.

공준호. Variable latency L1 data cache architecture design in multi-core processor under process variation. Journal of The Korea Society of Computer and Information, 20(9), 1-10.

공준호. Variable latency L1 data cache architecture design in multi-core processor under process variation. Journal of The Korea Society of Computer and Information. 2015; 20(9) 1-10.

공준호. Variable latency L1 data cache architecture design in multi-core processor under process variation. 2015; 20(9), 1-10.

공준호. "Variable latency L1 data cache architecture design in multi-core processor under process variation" Journal of The Korea Society of Computer and Information 20, no.9 (2015) : 1-10.