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Dead Block-Aware Adaptive Write Scheme for MLC STT-MRAM Caches

  • Journal of The Korea Society of Computer and Information
  • Abbr : JKSCI
  • 2020, 25(3), pp.1-9
  • DOI : 10.9708/jksci.2020.25.03.001
  • Publisher : The Korean Society Of Computer And Information
  • Research Area : Engineering > Computer Science
  • Received : February 11, 2020
  • Accepted : March 3, 2020
  • Published : March 31, 2020

HONG, SEOKIN 1

1경북대학교

Accredited

ABSTRACT

In this paper, we propose an efficient adaptive write scheme that improves the performance of write operation in MLC STT-MRAM caches. The key idea of the proposed scheme is to perform the write operation fast if the target MLC STT-MRAM cells contain a dead block. Even if the fast write operation on the MLC STT-MRAM evicts a cache block from the MLC STT-MRAM cells, its performance impact is low if the evicted block is a dead block which is not used in the future. Through experimental evaluation with a memory simulator, we show that the proposed adaptive write scheme improves the performance of the MLC STT-MRAM caches by 17% on average.

Citation status

* References for papers published after 2022 are currently being built.

This paper was written with support from the National Research Foundation of Korea.