Dead Block-Aware Adaptive Write Scheme for MLC STT-MRAM Caches (MLC STT-MRAM Cache을 위한 Dead Block 탐지 기반의 적응형 쓰기 기법)

HONG， SEOKIN (홍석인)

doi:10.9708/jksci.2020.25.03.001

Dead Block-Aware Adaptive Write Scheme for MLC STT-MRAM Caches

Journal of The Korea Society of Computer and Information
Abbr : JKSCI
2020, 25(3), pp.1-9
DOI : 10.9708/jksci.2020.25.03.001
Publisher : The Korean Society Of Computer And Information
Research Area : Engineering > Computer Science
Received : February 11, 2020
Accepted : March 3, 2020
Published : March 31, 2020

HONG， SEOKIN ¹

¹경북대학교

Accredited

ABSTRACT

In this paper, we propose an efficient adaptive write scheme that improves the performance of write operation in MLC STT-MRAM caches. The key idea of the proposed scheme is to perform the write operation fast if the target MLC STT-MRAM cells contain a dead block. Even if the fast write operation on the MLC STT-MRAM evicts a cache block from the MLC STT-MRAM cells, its performance impact is low if the evicted block is a dead block which is not used in the future. Through experimental evaluation with a memory simulator, we show that the proposed adaptive write scheme improves the performance of the MLC STT-MRAM caches by 17% on average.

KEYWORDS

STT-MRAM, Cache, Memory, Microprocessor, Dead Block, Simulation

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* References for papers published after 2023 are currently being built.

[confproc] Suock Chung / 2010 / Fully integrated 54nm STT-RAM with the smallest bit cell dimension for high density memory application / Proceedings of 2010 International Electron Devices Meeting : 12.7.1~12.7.4

[confproc] T. Ishigaki / 2010 / A multi-level-cell spin-transfer torque memory with series-stacked magnetotunnel junctions / Proceedings of 2010 Symposium on VLSI Technology : 47~48

[confproc] Lei Jiang / 2012 / Constructing large and fast multi-level cell STT-MRAM based cache for embedded processors / Proceedings of the 49th Annual Design Automation Conference : 907~912

[confproc] Y. Chen / 2010 / Access scheme of Multi-Level Cell Spin-Transfer Torque Random Access Memory and its optimization / Proceedings of 53rd IEEE International Midwest Symposium on Circuits and Systems : 1109~1112

[confproc] X. Bi / 2013 / Unleashing the potential of MLC STT-RAM caches / Proceedings of 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) : 429~436

[confproc] J. Wang / 2014 / Optimizing MLC-based STT-RAM caches by dynamic block size reconfiguration / Proceedings of 2014 IEEE 32nd International Conference on Computer Design (ICCD) : 133~138

[confproc] S. Hong / 2014 / Ternary cache: Three-valued MLC STT-RAM caches / Proceedings of 2014 IEEE 32nd International Conference on Computer Design (ICCD) : 83~89

[confproc] J. Xu / 2017 / Encoding Separately: An Energy-Efficient Write Scheme for MLC STT-RAM / Proceedings of 2017 IEEE International Conference on Computer Design (ICCD) : 581~584

[journal] Xiuyuan Bi / 2017 / Cross-Layer Optimization for Multilevel Cell STT-RAM Caches / IEEE Transactions on Very Large Scale Integration (VLSI) Systems / Institute of Electrical and Electronics Engineers (IEEE) 25(6) : 1807~1820

[journal] Muhammad Avais Qureshi / 2019 / A Restore-Free Mode for MLC STT-RAM Caches / IEEE Transactions on Very Large Scale Integration (VLSI) Systems / Institute of Electrical and Electronics Engineers (IEEE) 27(6) : 1465~1469

[confproc] S. M. Khan / 2010 / Sampling Dead Block Prediction for Last-Level Caches / Proceedings of 43rd Annual IEEE/ACM International Symposium on Microarchitecture : 175~186

[confproc] An-Chow Lai / 2001 / Dead-block prediction & dead-block correlating prefetchers / Proceedings of 28th Annual International Symposium on Computer Architecture : 144~154

[confproc] Haiming Liu / 2008 / Cache bursts : A new approach for eliminating dead blocks and increasing cache efficiency / Proceedings of the IEEE/ACM International Symposium on Microarchitecture : 222~233

[journal] M. Kharbutli / 2008 / Counter-Based Cache Replacement and Bypassing Algorithms / IEEE Transactions on Computers / Institute of Electrical and Electronics Engineers (IEEE) 57(4) : 433~447

[confproc] Zhigang Hu / 2003 / Timekeeping techniques for predicting and optimizing memory behavior / Proceedings of 2003 IEEE International Solid-State Circuits Conference : 166~485

[journal] Jaume Abella / 2005 / IATAC: a smart predictor to turn-off L2 cache lines / ACM Transactions on Architecture and Code Optimization / Association for Computing Machinery (ACM) 2(1) : 55~77

[confproc] L. Liu / 2017 / Building energy-efficient multi-level cell STT-RAM caches with data compression / Proceedings of 22nd Asia and South Pacific Design Automation Conference (ASP-DAC) : 751~756

[report] N. Chatterjee / 2012 / USIMM: The Utah Simulated Memory Module, tech / Univ. of Utah

This paper was written with support from the National Research Foundation of Korea.

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Journal of The Korea Society of Computer and Information 2023 KCI Impact Factor : 0.65

Dead Block-Aware Adaptive Write Scheme for MLC STT-MRAM Caches

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* References for papers published after 2023 are currently being built.

Journal of The Korea Society of Computer and Information 2023 KCI Impact Factor : 0.65

Dead Block-Aware Adaptive Write Scheme for MLC STT-MRAM Caches

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KEYWORDS

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* References for papers published after 2023 are currently being built.