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A Study on the Real-Time Visual Debugging of Hierarchically Designed Logic Circuits

  • Journal of Software Assessment and Valuation
  • Abbr : JSAV
  • 2022, 18(1), pp.71-78
  • DOI : 10.29056/jsav.2022.06.09
  • Publisher : Korea Software Assessment and Valuation Society
  • Research Area : Engineering > Computer Science
  • Received : June 2, 2022
  • Accepted : June 20, 2022
  • Published : June 30, 2022

Jang-Geun Ki 1 Kwon Kee Young 1

1공주대학교

Accredited

ABSTRACT

Rapid changes have been taking place throughout society due to the development and deployment of various personal mobile portable terminals and communication networks such as 5G wireless communication and high-speed Internet. In the case of education field, learning through online virtual experiment is also being attempted in experimental subjects, which were representative offline education subjects. In order to increase the educational effect in such online education, it is essential to develop various contents and check visually the results of virtual experiments. This paper describes the implementation of a circuit simulator that enables real time visual confirmation of the circuit operation of the desired layer when designing a hierarchical digital logic circuit. The developed simulator was designed to visually confirm the operation of the circuit by operating circuit elements of each layer in real time using object-oriented and event-driven programming techniques and displaying the results on the screen, and its usefulness was verified by applying various hierarchical design circuits.

Citation status

* References for papers published after 2022 are currently being built.