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@article{ART002850726},
author={Ki Jang Geun and Kwon Kee Young},
title={A Study on the Real-Time Visual Debugging of Hierarchically Designed Logic Circuits},
journal={Journal of Software Assessment and Valuation},
issn={2092-8114},
year={2022},
volume={18},
number={1},
pages={71-78},
doi={10.29056/jsav.2022.06.09}

TY - JOUR
AU - Ki Jang Geun
AU - Kwon Kee Young
TI - A Study on the Real-Time Visual Debugging of Hierarchically Designed Logic Circuits
JO - Journal of Software Assessment and Valuation
PY - 2022
VL - 18
IS - 1
PB - Korea Software Assessment and Valuation Society
SP - 71
EP - 78
SN - 2092-8114
AB - Rapid changes have been taking place throughout society due to the development and deployment of various personal mobile portable terminals and communication networks such as 5G wireless communication and high-speed Internet. In the case of education field, learning through online virtual experiment is also being attempted in experimental subjects, which were representative offline education subjects. In order to increase the educational effect in such online education, it is essential to develop various contents and check visually the results of virtual experiments. This paper describes the implementation of a circuit simulator that enables real time visual confirmation of the circuit operation of the desired layer when designing a hierarchical digital logic circuit. The developed simulator was designed to visually confirm the operation of the circuit by operating circuit elements of each layer in real time using object-oriented and event-driven programming techniques and displaying the results on the screen, and its usefulness was verified by applying various hierarchical design circuits.
KW - hierarchical design;logic circuit;simulation;visual debugging;engineering education
DO - 10.29056/jsav.2022.06.09
ER -

Ki Jang Geun and Kwon Kee Young. (2022). A Study on the Real-Time Visual Debugging of Hierarchically Designed Logic Circuits. Journal of Software Assessment and Valuation, 18(1), 71-78.

Ki Jang Geun and Kwon Kee Young. 2022, "A Study on the Real-Time Visual Debugging of Hierarchically Designed Logic Circuits", Journal of Software Assessment and Valuation, vol.18, no.1 pp.71-78. Available from: doi:10.29056/jsav.2022.06.09

Ki Jang Geun, Kwon Kee Young "A Study on the Real-Time Visual Debugging of Hierarchically Designed Logic Circuits" Journal of Software Assessment and Valuation 18.1 pp.71-78 (2022) : 71.

Ki Jang Geun, Kwon Kee Young. A Study on the Real-Time Visual Debugging of Hierarchically Designed Logic Circuits. 2022; 18(1), 71-78. Available from: doi:10.29056/jsav.2022.06.09

Ki Jang Geun and Kwon Kee Young. "A Study on the Real-Time Visual Debugging of Hierarchically Designed Logic Circuits" Journal of Software Assessment and Valuation 18, no.1 (2022) : 71-78.doi: 10.29056/jsav.2022.06.09

Ki Jang Geun; Kwon Kee Young. A Study on the Real-Time Visual Debugging of Hierarchically Designed Logic Circuits. Journal of Software Assessment and Valuation, 18(1), 71-78. doi: 10.29056/jsav.2022.06.09

Ki Jang Geun; Kwon Kee Young. A Study on the Real-Time Visual Debugging of Hierarchically Designed Logic Circuits. Journal of Software Assessment and Valuation. 2022; 18(1) 71-78. doi: 10.29056/jsav.2022.06.09

Ki Jang Geun, Kwon Kee Young. A Study on the Real-Time Visual Debugging of Hierarchically Designed Logic Circuits. 2022; 18(1), 71-78. Available from: doi:10.29056/jsav.2022.06.09

Ki Jang Geun and Kwon Kee Young. "A Study on the Real-Time Visual Debugging of Hierarchically Designed Logic Circuits" Journal of Software Assessment and Valuation 18, no.1 (2022) : 71-78.doi: 10.29056/jsav.2022.06.09