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A Study on Binary CDMA System Correlator Design for High-Speed Acquisition Processing

  • Journal of The Korea Society of Computer and Information
  • Abbr : JKSCI
  • 2007, 12(1), pp.157-162
  • Publisher : The Korean Society Of Computer And Information
  • Research Area : Engineering > Computer Science

Lee, Seon-Keun 1 정우열 2

1원광대학교
2한려대학교

Accredited

ABSTRACT

Because output of multi-code CDMA system adapted high speed data transmission becoming multi-level system use linear amplifier in output stage and complex output signal. Therefore, Multi-Code CDMA system has shortcoming of high price, high complexity etc.. Binary CDMA technology that allow fetters in existing CDMA technology to supplement this shortcoming proposed. In binary CDMA system When correlator process high speed data, bottle-neck phenomenon is happened on synchronization acquisition process, it is very important parameter. Because existent correlator must there be advantage that power consumption is small but flow addition of several stages to receive correlation's value, the processing speed has disadvantage because the operation amount is much. Therefore in this paper, proposed correlator has characteristic such as data is able to high speed processing, chip area is independent and power consumption is constant in structure in binary CDMA system.

Citation status

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