@article{ART001175770},
author={Jaejin Kim and Kwan Hyeong, Lee},
title={CPLD Low Power Technology Mapping using Reuse Module Selection under the Time Constraint},
journal={Journal of The Korea Society of Computer and Information},
issn={1598-849X},
year={2006},
volume={11},
number={3},
pages={161-166}
TY - JOUR
AU - Jaejin Kim
AU - Kwan Hyeong, Lee
TI - CPLD Low Power Technology Mapping using Reuse Module Selection under the Time Constraint
JO - Journal of The Korea Society of Computer and Information
PY - 2006
VL - 11
IS - 3
PB - The Korean Society Of Computer And Information
SP - 161
EP - 166
SN - 1598-849X
AB - In this paper, CPLD low power technology mapping using reuse module selection under the time constraint is proposed. Traditional high-level synthesis do not allow reuse of complex, realistic datapath component during the task of scheduling. On the other hand, the proposed algorithm is able to approach a productivity of the design the low power to reuse which given a library of user-defined datapath component and to share of resource sharing on the switching activity in a shared resource. Also, we are obtainable the optimal the scheduling result in experimental results of our using chaining and multi-cycling in the scheduling techniques. Low power circuit make using CPLD technology mapping algorithm for selection reuse module by scheduling
KW - CPLD Low power technology mapping;the time constraint;reuse;scheduling
DO -
UR -
ER -
Jaejin Kim and Kwan Hyeong, Lee. (2006). CPLD Low Power Technology Mapping using Reuse Module Selection under the Time Constraint. Journal of The Korea Society of Computer and Information, 11(3), 161-166.
Jaejin Kim and Kwan Hyeong, Lee. 2006, "CPLD Low Power Technology Mapping using Reuse Module Selection under the Time Constraint", Journal of The Korea Society of Computer and Information, vol.11, no.3 pp.161-166.
Jaejin Kim, Kwan Hyeong, Lee "CPLD Low Power Technology Mapping using Reuse Module Selection under the Time Constraint" Journal of The Korea Society of Computer and Information 11.3 pp.161-166 (2006) : 161.
Jaejin Kim, Kwan Hyeong, Lee. CPLD Low Power Technology Mapping using Reuse Module Selection under the Time Constraint. 2006; 11(3), 161-166.
Jaejin Kim and Kwan Hyeong, Lee. "CPLD Low Power Technology Mapping using Reuse Module Selection under the Time Constraint" Journal of The Korea Society of Computer and Information 11, no.3 (2006) : 161-166.
Jaejin Kim; Kwan Hyeong, Lee. CPLD Low Power Technology Mapping using Reuse Module Selection under the Time Constraint. Journal of The Korea Society of Computer and Information, 11(3), 161-166.
Jaejin Kim; Kwan Hyeong, Lee. CPLD Low Power Technology Mapping using Reuse Module Selection under the Time Constraint. Journal of The Korea Society of Computer and Information. 2006; 11(3) 161-166.
Jaejin Kim, Kwan Hyeong, Lee. CPLD Low Power Technology Mapping using Reuse Module Selection under the Time Constraint. 2006; 11(3), 161-166.
Jaejin Kim and Kwan Hyeong, Lee. "CPLD Low Power Technology Mapping using Reuse Module Selection under the Time Constraint" Journal of The Korea Society of Computer and Information 11, no.3 (2006) : 161-166.
