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CPLD Low Power Technology Mapping using Reuse Module Selection under the Time Constraint

  • Journal of The Korea Society of Computer and Information
  • Abbr : JKSCI
  • 2006, 11(3), pp.161-166
  • Publisher : The Korean Society Of Computer And Information
  • Research Area : Engineering > Computer Science

Jaejin Kim 1 Kwan Hyeong, Lee 2

1강동대학교
2대진대학교

Candidate

ABSTRACT

In this paper, CPLD low power technology mapping using reuse module selection under the time constraint is proposed. Traditional high-level synthesis do not allow reuse of complex, realistic datapath component during the task of scheduling. On the other hand, the proposed algorithm is able to approach a productivity of the design the low power to reuse which given a library of user-defined datapath component and to share of resource sharing on the switching activity in a shared resource. Also, we are obtainable the optimal the scheduling result in experimental results of our using chaining and multi-cycling in the scheduling techniques. Low power circuit make using CPLD technology mapping algorithm for selection reuse module by scheduling

Citation status

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