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CLB-Based CPLD Low Power Technology Mapping Algorithm for Trade-off

  • Journal of The Korea Society of Computer and Information
  • Abbr : JKSCI
  • 2005, 10(2), pp.49-58
  • Publisher : The Korean Society Of Computer And Information
  • Research Area : Engineering > Computer Science

Jaejin Kim 1 Kwan Hyeong, Lee 2

1강동대학교
2대진대학교

Candidate

ABSTRACT

In this paper, a CLB-based CPLD low power technology mapping algorithm for trade-off is proposed. To perform low power technology mapping for CPLD, a given Boolean network has to be represented to DAG. The proposed algorithm consists of three step. In the first step, TD(Transition Density) calculation have to be performed. Total power consumption is obtained by calculating switching activity of each nodes in a DAG. In the second step, the feasible clusters are generated by considering the following conditions: the number of output, the number of input and the number of OR-terms for CLB within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. The proposed algorithm is examined by using benchmarks in SIS. In the case that the number of OR-terms is 5, the experiments results show reduction in the power consumption by 30.73% comparing with that of TEMPLA, and 17.11% comparing with that of PLAmap respectively

Citation status

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