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Development of selectable observation point test architecture in the Boundry Scan

  • Journal of The Korea Society of Computer and Information
  • Abbr : JKSCI
  • 2008, 13(4), pp.87-96
  • Publisher : The Korean Society Of Computer And Information
  • Research Area : Engineering > Computer Science

Chang-Hee Lee 1 장영식 1

1계명문화대학

Accredited

ABSTRACT

In this paper, we developed a selectable observation point test architecture and test procedure for clocked 4-bit synchronous counter circuit based on boundary scan architecture. To develope, we analyze the operation of Sample/Preload instruction on boundary scan architecture. The Sample/Preload instruction make possible to snapshot of outputs of CUT(circuit under test) at the specific time. But the changes of output of CUT during normal operation are not possible to observe using Sample/Preload in typical scan architecture. We suggested a selectable observation point test architecture that allows to select output of CUT and to observe of the changes of selected output of CUT during normal operation. The suggested a selectable observation point test architecture and test procedure is simulated by Altera Max 10.0. The simulation results of 4-bit counter shows the accurate operation and effectiveness of the proposed test architecture and procedure.

Citation status

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