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The Design and implementation of parallel processing system using the Nios® II embedded processor

  • Journal of The Korea Society of Computer and Information
  • Abbr : JKSCI
  • 2009, 14(11), pp.97-103
  • Publisher : The Korean Society Of Computer And Information
  • Research Area : Engineering > Computer Science

LEE SI HYUN 1

1동서울대학교

Accredited

ABSTRACT

In this thesis, we discuss the implementation of parallel processing system which is able to get a high degree of efficiency(size, cost, performance and flexibility) by using Nios® II(32bit RISC(Reduced Instruction Set Computer) processor) embedded processor in DE2-70® reference board. The designed parallel processing system is master-slave, shared memory and MIMD(Multiple Instruction-Multiple Data stream) architecture with 4-processor. For performance test of system, N-point FFT is used. The result is represented speed-up as follow; in the case of using 2-processor(core), speed-up is shown as average 1.8 times as 1-processor's. When 4-processor, the speed-up is shown as average 2.4 times as it's.

Citation status

* References for papers published after 2022 are currently being built.