@article{ART001394127},
author={LEE SI HYUN},
title={The Design and implementation of parallel processing system using the Nios® II embedded processor},
journal={Journal of The Korea Society of Computer and Information},
issn={1598-849X},
year={2009},
volume={14},
number={11},
pages={97-103}
TY - JOUR
AU - LEE SI HYUN
TI - The Design and implementation of parallel processing system using the Nios® II embedded processor
JO - Journal of The Korea Society of Computer and Information
PY - 2009
VL - 14
IS - 11
PB - The Korean Society Of Computer And Information
SP - 97
EP - 103
SN - 1598-849X
AB - In this thesis, we discuss the implementation of parallel processing system which is able to get a high degree of efficiency(size, cost, performance and flexibility) by using Nios® II(32bit RISC(Reduced Instruction Set Computer) processor) embedded processor in DE2-70® reference board. The designed parallel processing system is master-slave, shared memory and MIMD(Multiple Instruction-Multiple Data stream) architecture with 4-processor. For performance test of system, N-point FFT is used. The result is represented speed-up as follow; in the case of using 2-processor(core), speed-up is shown as average 1.8 times as 1-processor's. When 4-processor, the speed-up is shown as average 2.4 times as it's.
KW - Parallel processing system;FPGA;SoC;RISC
DO -
UR -
ER -
LEE SI HYUN. (2009). The Design and implementation of parallel processing system using the Nios® II embedded processor. Journal of The Korea Society of Computer and Information, 14(11), 97-103.
LEE SI HYUN. 2009, "The Design and implementation of parallel processing system using the Nios® II embedded processor", Journal of The Korea Society of Computer and Information, vol.14, no.11 pp.97-103.
LEE SI HYUN "The Design and implementation of parallel processing system using the Nios® II embedded processor" Journal of The Korea Society of Computer and Information 14.11 pp.97-103 (2009) : 97.
LEE SI HYUN. The Design and implementation of parallel processing system using the Nios® II embedded processor. 2009; 14(11), 97-103.
LEE SI HYUN. "The Design and implementation of parallel processing system using the Nios® II embedded processor" Journal of The Korea Society of Computer and Information 14, no.11 (2009) : 97-103.
LEE SI HYUN. The Design and implementation of parallel processing system using the Nios® II embedded processor. Journal of The Korea Society of Computer and Information, 14(11), 97-103.
LEE SI HYUN. The Design and implementation of parallel processing system using the Nios® II embedded processor. Journal of The Korea Society of Computer and Information. 2009; 14(11) 97-103.
LEE SI HYUN. The Design and implementation of parallel processing system using the Nios® II embedded processor. 2009; 14(11), 97-103.
LEE SI HYUN. "The Design and implementation of parallel processing system using the Nios® II embedded processor" Journal of The Korea Society of Computer and Information 14, no.11 (2009) : 97-103.
