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@article{ART001407467},
author={박영진 and 김종면 and 김철홍},
title={Low-power Filter Cache Design Technique for Multicore Processors},
journal={Journal of The Korea Society of Computer and Information},
issn={1598-849X},
year={2009},
volume={14},
number={12},
pages={9-16}

TY - JOUR
AU - 박영진
AU - 김종면
AU - 김철홍
TI - Low-power Filter Cache Design Technique for Multicore Processors
JO - Journal of The Korea Society of Computer and Information
PY - 2009
VL - 14
IS - 12
PB - The Korean Society Of Computer And Information
SP - 9
EP - 16
SN - 1598-849X
AB - Energy consumption as well as performance should be considered when designing up-to-date multicore processors. In this paper, we propose new design technique to reduce the energy consumption in the instruction cache for multicore processors by using modified filter cache. The filter cache has been recognized as one of the most energy-efficient design techniques for singlecore processors. The energy consumed in the instruction cache accounts for a significant portion of total processor energy consumption. Therefore, energy-aware instruction cache design techniques are essential to reduce the energy consumption in a multicore processor. The proposed technique reduces the energy consumption in the instruction cache for multicore processors by reducing the number of accesses to the level-1 instruction cache. We evaluate the proposed design using a simulation infrastructure based on SimpleScalar and CACTI. Simulation results show that the proposed architecture reduces the energy consumption in the instruction cache for multicore processors by up to 3.4% compared to the conventional filter cache architecture. Moreover, the proposed architecture shows better performance over the conventional filter cache architecture.
KW - 멀티 코어 프로세서(Multicore Processor);명령어 캐쉬(Instruction Cache);희생 캐쉬(Victim Cache);전력 소모량(Energy Consumption)
DO -
UR -
ER -

박영진, 김종면 and 김철홍. (2009). Low-power Filter Cache Design Technique for Multicore Processors. Journal of The Korea Society of Computer and Information, 14(12), 9-16.

박영진, 김종면 and 김철홍. 2009, "Low-power Filter Cache Design Technique for Multicore Processors", Journal of The Korea Society of Computer and Information, vol.14, no.12 pp.9-16.

박영진, 김종면, 김철홍 "Low-power Filter Cache Design Technique for Multicore Processors" Journal of The Korea Society of Computer and Information 14.12 pp.9-16 (2009) : 9.

박영진, 김종면, 김철홍. Low-power Filter Cache Design Technique for Multicore Processors. 2009; 14(12), 9-16.

박영진, 김종면 and 김철홍. "Low-power Filter Cache Design Technique for Multicore Processors" Journal of The Korea Society of Computer and Information 14, no.12 (2009) : 9-16.

박영진; 김종면; 김철홍. Low-power Filter Cache Design Technique for Multicore Processors. Journal of The Korea Society of Computer and Information, 14(12), 9-16.

박영진; 김종면; 김철홍. Low-power Filter Cache Design Technique for Multicore Processors. Journal of The Korea Society of Computer and Information. 2009; 14(12) 9-16.

박영진, 김종면, 김철홍. Low-power Filter Cache Design Technique for Multicore Processors. 2009; 14(12), 9-16.

박영진, 김종면 and 김철홍. "Low-power Filter Cache Design Technique for Multicore Processors" Journal of The Korea Society of Computer and Information 14, no.12 (2009) : 9-16.