Analysis on the Temperature of 3D Multi-core Processors according to Vertical Placement of Core and L2 Cache (코어와 L2 캐쉬의 수직적 배치 관계에 따른 3차원 멀티코어 프로세서의 온도 분석)

손동오; 안진우; PARK JAE  HYUNG (박재형); 김종면; 김철홍

Analysis on the Temperature of 3D Multi-core Processors according to Vertical Placement of Core and L2 Cache

Journal of The Korea Society of Computer and Information
Abbr : JKSCI
2011, 16(6), pp.1-10
Publisher : The Korean Society Of Computer And Information
Research Area : Engineering > Computer Science

손동오 ¹, 안진우 ¹, PARK JAE HYUNG ¹, 김종면 ², 김철홍 ¹

¹전남대학교
²울산대학교

Accredited

ABSTRACT

In designing multi-core processors, interconnection delay is one of the major constraints in performance improvement. To solve this problem, the 3-dimensional integration technology has been adopted in designing multi-core processors. The 3D multi-core architecture can reduce the physical wire length by stacking cores vertically, leading to reduced interconnection delay and reduced power consumption. However, the power density of 3D multi-core architecture is increased significantly compared to the traditional 2D multi-core architecture, resulting in the increased temperature of the processor. In this paper, the floorplan methods which change the forms of vertical placement of the core and the level-2 cache are analyzed to solve the thermal problems in 3D multi-core processors. According to the experimental results, it is an effective way to reduce the temperature in the processor that the core and the level-2 cache are stacked adjacently. Compared to the floorplan where cores are stacked adjacently to each other, the floorplan where the core is stacked adjacently to the level-2 cache can reduce the temperature by 22% in the case of 4-layers, and by 13% in the case of 2-layers.

KEYWORDS

multi-core processor, 3D integrated circuits, temperature, floorplan

Citation status

* References for papers published after 2023 are currently being built.

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This paper was written with support from the National Research Foundation of Korea.

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