@article{ART001560459},
author={손동오 and 안진우 and PARK JAE HYUNG and 김종면 and 김철홍},
title={Analysis on the Temperature of 3D Multi-core Processors according to Vertical Placement of Core and L2 Cache},
journal={Journal of The Korea Society of Computer and Information},
issn={1598-849X},
year={2011},
volume={16},
number={6},
pages={1-10}
TY - JOUR
AU - 손동오
AU - 안진우
AU - PARK JAE HYUNG
AU - 김종면
AU - 김철홍
TI - Analysis on the Temperature of 3D Multi-core Processors according to Vertical Placement of Core and L2 Cache
JO - Journal of The Korea Society of Computer and Information
PY - 2011
VL - 16
IS - 6
PB - The Korean Society Of Computer And Information
SP - 1
EP - 10
SN - 1598-849X
AB - In designing multi-core processors, interconnection delay is one of the major constraints in performance improvement. To solve this problem, the 3-dimensional integration technology has been adopted in designing multi-core processors. The 3D multi-core architecture can reduce the physical wire length by stacking cores vertically, leading to reduced interconnection delay and reduced power consumption. However, the power density of 3D multi-core architecture is increased significantly compared to the traditional 2D multi-core architecture, resulting in the increased temperature of the processor. In this paper, the floorplan methods which change the forms of vertical placement of the core and the level-2 cache are analyzed to solve the thermal problems in 3D multi-core processors. According to the experimental results, it is an effective way to reduce the temperature in the processor that the core and the level-2 cache are stacked adjacently.
Compared to the floorplan where cores are stacked adjacently to each other, the floorplan where the core is stacked adjacently to the level-2 cache can reduce the temperature by 22% in the case of 4-layers, and by 13% in the case of 2-layers.
KW - multi-core processor;3D integrated circuits;temperature;floorplan
DO -
UR -
ER -
손동오, 안진우, PARK JAE HYUNG, 김종면 and 김철홍. (2011). Analysis on the Temperature of 3D Multi-core Processors according to Vertical Placement of Core and L2 Cache. Journal of The Korea Society of Computer and Information, 16(6), 1-10.
손동오, 안진우, PARK JAE HYUNG, 김종면 and 김철홍. 2011, "Analysis on the Temperature of 3D Multi-core Processors according to Vertical Placement of Core and L2 Cache", Journal of The Korea Society of Computer and Information, vol.16, no.6 pp.1-10.
손동오, 안진우, PARK JAE HYUNG, 김종면, 김철홍 "Analysis on the Temperature of 3D Multi-core Processors according to Vertical Placement of Core and L2 Cache" Journal of The Korea Society of Computer and Information 16.6 pp.1-10 (2011) : 1.
손동오, 안진우, PARK JAE HYUNG, 김종면, 김철홍. Analysis on the Temperature of 3D Multi-core Processors according to Vertical Placement of Core and L2 Cache. 2011; 16(6), 1-10.
손동오, 안진우, PARK JAE HYUNG, 김종면 and 김철홍. "Analysis on the Temperature of 3D Multi-core Processors according to Vertical Placement of Core and L2 Cache" Journal of The Korea Society of Computer and Information 16, no.6 (2011) : 1-10.
손동오; 안진우; PARK JAE HYUNG; 김종면; 김철홍. Analysis on the Temperature of 3D Multi-core Processors according to Vertical Placement of Core and L2 Cache. Journal of The Korea Society of Computer and Information, 16(6), 1-10.
손동오; 안진우; PARK JAE HYUNG; 김종면; 김철홍. Analysis on the Temperature of 3D Multi-core Processors according to Vertical Placement of Core and L2 Cache. Journal of The Korea Society of Computer and Information. 2011; 16(6) 1-10.
손동오, 안진우, PARK JAE HYUNG, 김종면, 김철홍. Analysis on the Temperature of 3D Multi-core Processors according to Vertical Placement of Core and L2 Cache. 2011; 16(6), 1-10.
손동오, 안진우, PARK JAE HYUNG, 김종면 and 김철홍. "Analysis on the Temperature of 3D Multi-core Processors according to Vertical Placement of Core and L2 Cache" Journal of The Korea Society of Computer and Information 16, no.6 (2011) : 1-10.