A Study on the Construction of Parallel Multiplier over GF(2m) (GF(2m) 상에서의 병렬 승산기 설계에 관한 연구)

Han， Sung-il (한성일)

A Study on the Construction of Parallel Multiplier over GF(2m)

Journal of The Korea Society of Computer and Information
Abbr : JKSCI
2012, 17(3), pp.1-10
Publisher : The Korean Society Of Computer And Information
Research Area : Engineering > Computer Science

Han， Sung-il ¹

¹인덕대학교

Accredited

ABSTRACT

A low-complexity Multiplication over GF(2m) and multiplier circuit has been proposed by using cyclic-shift coefficients and the irreducible trinomial. The proposed circuit has the parallel input/output architecture and shows the lower-complexity than others with the characteristics of the cyclic-shift coefficients and the irreducible trinomial modular computation. The proposed multiplier is composed of 2-input AND gates and 2-input XOR gates without the memories and switches. And the minimum propagation delay is . The Proposed circuit architecture is well suited to VLSI implementation because it is simple, regular and modular.

KEYWORDS

Finite field, Irreducible trinomial, multiplier, Finite field multiplication

Citation status

* References for papers published after 2023 are currently being built.

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