AMEX: Extending AddressingMode of 16-bit Thumb Instruction Set Architecture (AMEX: 16비트 Thumb 명령어 집합 구조의 주소 지정 방식 확장)

김대환

AMEX: Extending AddressingMode of 16-bit Thumb Instruction Set Architecture

Journal of The Korea Society of Computer and Information
Abbr : JKSCI
2012, 17(11), pp.1-10
Publisher : The Korean Society Of Computer And Information
Research Area : Engineering > Computer Science

김대환 ¹

¹수원과학대학교

Accredited

ABSTRACT

In this paper, the extension of the addressing mode in the 16-bit Thumb instruction set architecture is proposed to improve the performance of 16-bit Thumb code. The key idea of the proposed approach is the introduction of newaddressingmodes formore frequent instructions by using the saved bits fromthe reduction of the register fields in less frequently used instructions. The proposed approach adopts efficient addressing modes fromthe 32-bit ARMarchitecture, which is the superset of the 16-bit Thumb architecture. To speed up access to a data list, scaled register offset addressingmode and post-indexed addressingmode are introduced for load and store instructions. Experiments showthat the proposed approach improves performance by an average of 8.5% when compared to the conventional approach.

KEYWORDS

Instruction set design, Addressing mode, Embedded processor, Thumb, ARM

Citation status

* References for papers published after 2023 are currently being built.

[journal] S. Segars / 1995 / Embedded control problems, Thumb, andtheARM7TDMI / IEEE Micro 15(5) : 22~30

[report] K. Kissell / 1997 / MIPS16 : High-Density MIPS for the EmbeddedMarket / Technical report, Silicon Graphics MIPS Group

[book] Advanced RISCMachines Ltd / 2011 / ARMAnnual Report& Accounts 2011 / Advanced RISCMachines Ltd

[book] R. Phelan / 2003 / Improving ARMCodeDensity and Performance, In echnical report / Advanced RISCMachines Ltd.

[confproc] A. Krishnaswamy / 2005 / Efficient Use of Invisible Registers in Thumb Code / In Proc. of the 38th IEEE/ACMInternational SymposiumonMicroarchitecture : 30~42

[journal] A. Krishnaswamy / 2005 / Dynamic coalescing for 16-bit instructions / ACMTransaction on Embedded Computing System 4(1) : 3~37

[confproc] J. H. Lee / 2009 / Comparison of Bank ChangeMechanisms for Banked Reduced Encoding Architectures / In Proc. of the International Conference on Computational Science and Engineering 2 : 334~341

[journal] Y. -J. Kwon / 1999 / PARE : instruction set architecture for efficient code size reduction / IEE ElectronicsLetters 35(24) : 2098~2099

[confproc] L. Dong / 2006 / Multithreading extension for Thumb ISA and decoder support / In Proc. of the 5thWSEAS Int. Conf. on Electronics, Hardware, Wireless andOptical Communications : 78~81

[confproc] X. H. Xu / 2003 / ARM/THUMB code compression for embedded systems / In Proc. of 15th Int. Conf. onMicroelectronics : 32~35

[confproc] A. M. Fiskiran / 2001 / Performance Impact of AddressingModes on Encryption Algorithms / In Proc. of the International Conference on Computer Design (ICCD 2001) : 542~545

[confproc] B. Li / 2002 / Bit Section Instruction Set Extension of ARMfor Embedded Applications / In Proc. of International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) : 69~78

[confproc] H. -J. Cheng / 2010 / Trading Conditional Execution for More Registers on ARMProcessors / In Proc. of the 8th IEEE/IFIP Int. Conf. on Embedded and Ubiquitous Computing (EUC) : 53~59

[confproc] H. -H. Chiang / 2012 / Doubling the Number of Registers on ARMProcessors / In Proc. of the 16th Workshop onInteraction between Compilers and ComputerArchitectures (INTERACT-16)

[confproc] S. Bartolini / 2004 / A Performance Evaluation of ARMISA Extension for Elliptic Curve Cryptography over Binary Finite Fields / In Proc. of 16th Symposiumon Computer Architecture and High Performance Computing : 238~245

[book] Hedley Francis / 2001 / ARMDSP-Enhanced Extensions / ARM Ltd

[book] ARM Ltd / 2001 / ARM Jazelle Technology

[book] J. Rokov / 2010 / ARM Architecture and Multimedia Applications / RIZ-Transmitters Co

[book] ARMLtd / 2009 / IntroducingNEON™Development Article

[journal] J. Goodacre / 2005 / Parallelismand the ARM instruction set architecture / Computer 38(7) : 42~50

[journal] 강성모 / 2012 / Multimedia Extension Instructions and Optimal Many-core Processor Architecture Exploration for Portable Ultrasonic Image Processing / 한국컴퓨터정보학회논문지 / 한국컴퓨터정보학회 17(8) : 1~10

[journal] 정용범 / 2011 / Performance Evaluation and Verification of MMX-type Instructions on an Embedded Parallel Processor / 한국컴퓨터정보학회논문지 / 한국컴퓨터정보학회 16(10) : 11~22

[confproc] J. Lee / 2007 / FaCSim : A Fast and Cycle-Accurate Architecture Simulator for Embedded Systems / In Proc. of the Int. Conf. on Languages, Compilers, and Tools for Embedded Systems(LCTES'08) : 89~100

[confproc] A. Krishnaswamy / 2002 / Profile guided selection of armand thumb instructions / In Proc. of the ACM SIGPLAN Joint Conf. on Languages Compilers and Tools for Embedded Systems & Software and Compilers for Embedded Systems : 55~64

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