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Cache memory system for high performance CPU with 4GHz

  • Journal of The Korea Society of Computer and Information
  • Abbr : JKSCI
  • 2013, 18(2), pp.1-8
  • Publisher : The Korean Society Of Computer And Information
  • Research Area : Engineering > Computer Science

JUNG BOSUNG 1 Lee Jung Hoon 2

1경상대학교 ERI 제어계측공학과
2경상대학교

Accredited

ABSTRACT

TIn this paper, we propose a high performance L1 cache structure on the high clock CPU of 4GHz. The proposed cache memory consists of three parts, i.e., a direct-mapped cache to support fast access time, a two-way set associative buffer to exploit temporal locality, and a buffer-select table. The most recently accessed data is stored in the direct-mapped cache. If a data has a high probability of a repeated reference, when the data is replaced from the direct-mapped cache, the data is selectively stored into the two-way set associative buffer. For the high performance and low power consumption, we propose an one way among two ways set associative buffer is selectively accessed based on the buffer-select table(BST). According to simulation results, Energy * Delay product can improve about 45%, 70% and 75% compared with a direct mapped cache, a four-way set associative cache, and a victim cache with two times more space respectively.

Citation status

* References for papers published after 2023 are currently being built.