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Design of High-Speed Parallel Multiplier with All Coefficients 1’s of Primitive Polynomial over Finite Fields GF(2m)

  • Journal of The Korea Society of Computer and Information
  • Abbr : JKSCI
  • 2013, 18(2), pp.9-17
  • Publisher : The Korean Society Of Computer And Information
  • Research Area : Engineering > Computer Science

성현경 1

1상지대학교

Accredited

ABSTRACT

In this paper, we propose a new multiplication algorithm for two polynomials using primitive polynomial with all 1 of coefficient on finite fields GF(2m), and design the multiplier with high-speed parallel input-output module structure using the presented multiplication algorithm.The proposed multiplier is designed ㎡ same basic cells that have a 2-input XOR gate and a 2-input AND gate. Since the basic cell have no a latch circuit, the multiplicative circuit is very simple and is short the delay time DA+AX per cell unit. The proposed multiplier is easy to extend the circuit with large m having regularity and modularity by cell array, and is suitable to the implementation of VLSI circuit.

Citation status

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