@article{ART001790972},
author={김대환},
title={Parallel Branch Instruction Extension for Thumb-2 Instruction Set Architecture},
journal={Journal of The Korea Society of Computer and Information},
issn={1598-849X},
year={2013},
volume={18},
number={7},
pages={1-10}
TY - JOUR
AU - 김대환
TI - Parallel Branch Instruction Extension for Thumb-2 Instruction Set Architecture
JO - Journal of The Korea Society of Computer and Information
PY - 2013
VL - 18
IS - 7
PB - The Korean Society Of Computer And Information
SP - 1
EP - 10
SN - 1598-849X
AB - In this paper, the parallel branch instruction is proposed which executes a branch instruction and the frequently used instruction simultaneously to improve the performance of Thumb-2instruction set architecture. In the proposed approach, new 32-bit parallel branch instructions are introduced which combine 16-bit branch instruction with each of the frequently used 16-bit LOAD,ADD, MOV, STORE, and SUB instructions, respectively. To provide the encoding space of the new instructions, the register field in less frequently executed instructions is reduced, and the new instructions are encoded by using the saved bits. Experiments show that the proposed approach improves performance by an average of 8.0% when compared to the conventional approach.
KW - Instruction set design;Parallel branch instruction;Embedded processor;Thumb-2;ARM
DO -
UR -
ER -
김대환. (2013). Parallel Branch Instruction Extension for Thumb-2 Instruction Set Architecture. Journal of The Korea Society of Computer and Information, 18(7), 1-10.
김대환. 2013, "Parallel Branch Instruction Extension for Thumb-2 Instruction Set Architecture", Journal of The Korea Society of Computer and Information, vol.18, no.7 pp.1-10.
김대환 "Parallel Branch Instruction Extension for Thumb-2 Instruction Set Architecture" Journal of The Korea Society of Computer and Information 18.7 pp.1-10 (2013) : 1.
김대환. Parallel Branch Instruction Extension for Thumb-2 Instruction Set Architecture. 2013; 18(7), 1-10.
김대환. "Parallel Branch Instruction Extension for Thumb-2 Instruction Set Architecture" Journal of The Korea Society of Computer and Information 18, no.7 (2013) : 1-10.
김대환. Parallel Branch Instruction Extension for Thumb-2 Instruction Set Architecture. Journal of The Korea Society of Computer and Information, 18(7), 1-10.
김대환. Parallel Branch Instruction Extension for Thumb-2 Instruction Set Architecture. Journal of The Korea Society of Computer and Information. 2013; 18(7) 1-10.
김대환. Parallel Branch Instruction Extension for Thumb-2 Instruction Set Architecture. 2013; 18(7), 1-10.
김대환. "Parallel Branch Instruction Extension for Thumb-2 Instruction Set Architecture" Journal of The Korea Society of Computer and Information 18, no.7 (2013) : 1-10.