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Design of High-Speed Parallel Multiplier on Finite Fields GF(3m)

  • Journal of The Korea Society of Computer and Information
  • Abbr : JKSCI
  • 2015, 20(2), pp.1-10
  • Publisher : The Korean Society Of Computer And Information
  • Research Area : Engineering > Computer Science

성현경 1

1상지대학교

Accredited

ABSTRACT

In this paper, we propose a new multiplication algorithm for primitive polynomial with all 1 of coefficientin case that m is odd and even on finite fields GF(3m), and design the multiplier with parallelinput-output module structure using the presented multiplication algorithm. The proposed multiplier isdesigned (m+1)2 same basic cells. Since the basic cells have no a latch circuit, the multiplicativecircuit is very simple and is short the delay time TA+TX per cell unit. The proposed multiplier is easyto extend the circuit with large m having regularity and modularity by cell array, and is suitable to theimplementation of VLSI circuit.

Citation status

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