An Aging Measurement Scheme for Flash Memory Using LDPC Decoding Information

Taegeun Kang (강태근); Hyunbean Yi (이현빈)

doi:10.9708/jksci.2020.25.01.029

An Aging Measurement Scheme for Flash Memory Using LDPC Decoding Information

Journal of The Korea Society of Computer and Information
Abbr : JKSCI
2020, 25(1), pp.29-36
DOI : 10.9708/jksci.2020.25.01.029
Publisher : The Korean Society Of Computer And Information
Research Area : Engineering > Computer Science
Received : November 11, 2019
Accepted : January 14, 2020
Published : January 31, 2020

Taegeun Kang ¹, Hyunbean Yi ¹

¹한밭대학교

Accredited

ABSTRACT

Wear-leveling techniques and Error Correction Codes (ECCs) are essential for the improvement of the reliability and durability of flash memories. Low-Density Parity-Check (LDPC) codes have higher error correction capabilities than conventional ECCs and have been applied to various flash memory-based storage devices. Conventional wear-leveling schemes using only the number of Program/Erase (P/E) cycles are not enough to reflect the actual aging differences of flash memory components. This paper introduces an actual aging measurement scheme for flash memory wear-leveling using LDPC decoding information. Our analysis, using error-rates obtained from an flash memory module, shows that LDPC decoding information can represent the aging degree of each block. We also show the effectiveness of the wear-leveling based on the proposed scheme through wear-leveling simulation experiments.

KEYWORDS

Flash Memory, Wear-Leveling, ECC, LDPC Codes, Aging Measurement

Citation status

* References for papers published after 2023 are currently being built.

[book] R. Micheloni / 2008 / Error Correction Codes for Non-Volatile Memories / Springer

[book] J. C. Moreira / 2006 / Essentials of Error–Control Coding / John Wiley and Sons

[journal] R. G. Gallager / 1962 / Low Density Parity Check Codes / IRE Transactions on Information Theory 8(1) : 21~28

[journal] G. Dong / 2011 / On the Use of Soft-Decision Error-Correction Codes in NAND Flash Memory / IEEE Transactions on Circuits and Systems I 58(2) : 429~439

[journal] J. Kim / 2014 / Rate-0. 96 LDPC Decoding VLSI for Soft-Decision Error Correction of NAND Flash Memory / IEEE Transactions on Very Large Scale Integration(VLSI)Systems 22(5) : 1004~1015

[journal] Y. Cai / 2017 / Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives / Proceedings of the IEEE 105(9) : 1666~1704

[journal] R. Bez / 2003 / Introduction to Flash Memory / Proceedings of the IEEE 91(4) : 489~502

[confproc] N. Mielke / 2008 / Bit Error Rate in NAND Flash Memories / 2008IEEE International Reliability Physics Symposium : 9~19

[confproc] L. -P. Chang / 2007 / On Efficient Wear Leveling for Large-Scale Flash-Memory Storage Systems / Proceedings of the 2007 ACM symposium on Applied computing : 1126~1130

[confproc] Y. -H. Chang / 2007 / Endurance Enhancement of Flash-Memory Storage, Systems: An Efficient Static Wear Leveling Design / 2007 44th ACM/IEEE Design Automation Conference : 212~217

[confproc] M. Murugan / 2011 / Rejuvenator: A Static Wear Leveling Algorithm for NAND Flash Memory with Minimized Overhead / 2011 IEEE 27th Symposium on Mass Storage Systems and Technologies (MSST)

[journal] Y. Pan / 2013 / Error Rate-Based Wear-Leveling for Nand Flash Memory at Highly Scaled Technology Nodes / IEEE Transactions on Very Large Scale Integration(VLSI)Systems 21(7) : 1350~1354

[confproc] B. Peleato / 2015 / BER-Based Wear Leveling and Bad Block Management for NAND Flash / 2015 IEEE International Conference on Communications (ICC) : 295~300

[confproc] X. Shi / 2018 / Program Error Rate-based Wear Leveling for NAND Flash Memory / 2018 Design, Automation and Test in Europe Conference & Exhibition (DATE) : 1241~1246

[journal] M. Karimi / 2014 / On Characterization of Elementary Trapping Sets of Variable-Regular LDPC codes / IEEE Transactions on Information Theory 60(9) : 5188~5203

[journal] S. Laendner / 2007 / LDPC Codes Based on Latin Squares : Cycle Structure, Stopping Set, and Trapping Set Analysis / IEEE Transactions on Communications 55(2) : 303~312

[journal] M. P. C. Fossorier / 2004 / Quasi-Cyclic Low-Density Parity-Check Codes from Circulant Permutation Matrices / IEEE Transactions on Information Theory 50(8) : 1788~1793

[confproc] C. Yoon / 2007 / Arbitrary Bit Generation and Correction Technique for Encoding QC-LDPC Codes with Dual-Daigonal Parity Structure / 2007 IEEE Wireless Communications and Networking Conference : 663~667

[journal] J. Chen / 2005 / Reduced-Complexity Decoding of LDPC Codes / IEEE Transactions on Communications 53(8) : 1288~1299

This paper was written with support from the National Research Foundation of Korea.

KJCKorea
Journal Central

Journal of The Korea Society of Computer and Information 2023 KCI Impact Factor : 0.65

An Aging Measurement Scheme for Flash Memory Using LDPC Decoding Information

ABSTRACT

KEYWORDS

Citation status

* References for papers published after 2023 are currently being built.

Journal of The Korea Society of Computer and Information 2023 KCI Impact Factor : 0.65

An Aging Measurement Scheme for Flash Memory Using LDPC Decoding Information

ABSTRACT

KEYWORDS

Statistics

Tools

Issue List

Citation status

KCI Citation Counts (0)

REFERENCES (19) * References for papers published after 2023 are currently being built.

Search PDF

Citation

* References for papers published after 2023 are currently being built.