2020, Vol.25, No.1

Journal of The Korea Society of Computer and Information 2023 KCI Impact Factor : 0.65

pISSN : 1598-849X / eISSN : 2383-9945
https://journal.kci.go.kr/jksci

In this paper, we present a technique that executes MPI parallel programs, that are developed on processor-centric computer architecture, more efficiently on memory-centric computer architecture without program modification. The technique we present here improves performance by replacing low-speed data communication over the network of MPI library functions with high-speed data communication using the property called fast large shared memory of memory-centric computer architecture. The technique we present in the paper is implemented in two programs. The first program is a modified MPI library called MC-MPI-LIB that runs MPI parallel programs more efficiently on memory-centric computer architecture preserving the semantics of MPI library functions. The second program is a simulation program called MC-MPI-SIM that simulates the performance of memory-centric computer architecture on processor-centric computer architecture. We developed and tested the programs on distributed systems environment deployed on Docker based virtualization. We analyzed the performance of several MPI parallel programs and showed that we achieved better performance on memory-centric computer architecture. Especially we could see very high performance on the MPI parallel programs with high communication overhead.

In this paper, we propose a multiplexer based scheme that performs modular AB2 multiplication using redundant basis over finite field. Then we propose an efficient multiplexer based semi-systolic AB2 multiplier using proposed scheme. We derive a method that allows the multiplexers to perform the operations in the cell of the modular AB2 multiplier. The cell of the multiplier is implemented using multiplexers to reduce cell latency. As compared to the existing related structures, the proposed AB2 multiplier saves about 80.9%, 61.8%, 61.8%, and 9.5% AT complexity of the multipliers of Liu et al., Lee et al., Ting et al., and Kim-Kim, respectively. Therefore, the proposed multiplier is well suited for VLSI implementation and can be easily applied to various applications.

In this paper, a hybrid scheduling algorithm is proposed for CMS(Combat Management System) to improve QoS(Quality of Service) based on DWDRR(Dynamic Weighted Deficit Round Robin) and priority-based scheduling method. The main proposed scheme, DWDRR is method of packet transmission through giving weight by traffic of queue and priority. To demonstrate an usefulness of proposed algorithm through simulation, efficiency in special section of the proposed algorithm is proved. Therefore, We propose hybrid algorithm between existing algorithm and proposed algorithm. Also, to prevent frequent scheme conversion, a hysteresis method is applied. The proposed algorithm shows lower packet loss rate and delay in the same traffic than existing algorithm.