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Low-area Bit-parallel Systolic Array for Multiplication and Square over Finite Fields

  • Journal of The Korea Society of Computer and Information
  • Abbr : JKSCI
  • 2020, 25(2), pp.41-48
  • DOI : 10.9708/jksci.2020.25.02.041
  • Publisher : The Korean Society Of Computer And Information
  • Research Area : Engineering > Computer Science
  • Received : January 15, 2020
  • Accepted : February 7, 2020
  • Published : February 28, 2020

Keewon Kim 1

1단국대학교

Accredited

ABSTRACT

In this paper, we derive a common computational part in an algorithm that can simultaneously perform multiplication and square over finite fields, and propose a low-area bit-parallel systolic array that reduces hardware through sequential processing. The proposed systolic array has less space and area-time (AT) complexity than the existing related arrays. In detail, the proposed systolic array saves about 48% and 44% of Choi-Lee and Kim-Kim’s systolic arrays in terms of area complexity, and about 74% and 44% in AT complexity. Therefore, the proposed systolic array is suitable for VLSI implementation and can be applied as a basic component in hardware constrained environment such as IoT.

Citation status

* References for papers published after 2022 are currently being built.

This paper was written with support from the National Research Foundation of Korea.