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@article{ART001417377},
author={최홍준 and 양나라 and Jeong-A Lee and 김종면 and 김철홍},
title={Processor Design Technique for Low-Temperature Filter Cache},
journal={Journal of The Korea Society of Computer and Information},
issn={1598-849X},
year={2010},
volume={15},
number={1},
pages={1-12}

TY - JOUR
AU - 최홍준
AU - 양나라
AU - Jeong-A Lee
AU - 김종면
AU - 김철홍
TI - Processor Design Technique for Low-Temperature Filter Cache
JO - Journal of The Korea Society of Computer and Information
PY - 2010
VL - 15
IS - 1
PB - The Korean Society Of Computer And Information
SP - 1
EP - 12
SN - 1598-849X
AB - Recently, processor performance has been improved dramatically. Unfortunately, as the process technology scales down, energy consumption in a processor increases significantly whereas the processor performance continues to improve. Moreover, peak temperature in the processor increases dramatically due to the increased power density, resulting in serious thermal problem. For this reason, performance, energy consumption and thermal problem should be considered together when designing up-to-date processors. This paper proposes three modified filter cache schemes to alleviate the thermal problem in the filter cache, which is one of the most energy-efficient design techniques in the hierarchical memory systems : Bypass Filter Cache (BFC), Duplicated Filter Cache (DFC) and Partitioned Filter Cache (PFC). BFC scheme enables the direct access to the L1 cache when the temperature on the filter cache exceeds the threshold, leading to reduced temperature on the filter cache. DFC scheme lowers temperature on the filter cache by appending an additional filter cache to the existing filter cache. The filter cache for PFC scheme is composed of two half-size filter caches to lower the temperature on the filter cache by reducing the access frequency. According to our simulations using Wattch and Hotspot, the proposed partitioned filter cache shows the lowest peak temperature on the filter cache, leading to higher reliability in the processor.
KW - Embedded Processor;Filter Cache;Modified Filter Cache;Low-power Technique;Low-temperature Technique
DO -
UR -
ER -

최홍준, 양나라, Jeong-A Lee, 김종면 and 김철홍. (2010). Processor Design Technique for Low-Temperature Filter Cache. Journal of The Korea Society of Computer and Information, 15(1), 1-12.

최홍준, 양나라, Jeong-A Lee, 김종면 and 김철홍. 2010, "Processor Design Technique for Low-Temperature Filter Cache", Journal of The Korea Society of Computer and Information, vol.15, no.1 pp.1-12.

최홍준, 양나라, Jeong-A Lee, 김종면, 김철홍 "Processor Design Technique for Low-Temperature Filter Cache" Journal of The Korea Society of Computer and Information 15.1 pp.1-12 (2010) : 1.

최홍준, 양나라, Jeong-A Lee, 김종면, 김철홍. Processor Design Technique for Low-Temperature Filter Cache. 2010; 15(1), 1-12.

최홍준, 양나라, Jeong-A Lee, 김종면 and 김철홍. "Processor Design Technique for Low-Temperature Filter Cache" Journal of The Korea Society of Computer and Information 15, no.1 (2010) : 1-12.

최홍준; 양나라; Jeong-A Lee; 김종면; 김철홍. Processor Design Technique for Low-Temperature Filter Cache. Journal of The Korea Society of Computer and Information, 15(1), 1-12.

최홍준; 양나라; Jeong-A Lee; 김종면; 김철홍. Processor Design Technique for Low-Temperature Filter Cache. Journal of The Korea Society of Computer and Information. 2010; 15(1) 1-12.

최홍준, 양나라, Jeong-A Lee, 김종면, 김철홍. Processor Design Technique for Low-Temperature Filter Cache. 2010; 15(1), 1-12.

최홍준, 양나라, Jeong-A Lee, 김종면 and 김철홍. "Processor Design Technique for Low-Temperature Filter Cache" Journal of The Korea Society of Computer and Information 15, no.1 (2010) : 1-12.