Design of Run-time signal test architecture in IEEE 1149.1 (IEEE 1149.1의 실시간 신호 시험 구조 설계)

Kim Jeong Hong (김정홍); 장영식; Kim,Jae-Soo (김재수)

Design of Run-time signal test architecture in IEEE 1149.1

Journal of The Korea Society of Computer and Information
Abbr : JKSCI
2010, 15(1), pp.13-21
Publisher : The Korean Society Of Computer And Information
Research Area : Engineering > Computer Science

Kim Jeong Hong ¹, 장영식 ², Kim,Jae-Soo ¹

¹경북대학교
²계명문화대학

Accredited

ABSTRACT

IEEE 1149.1 test architecture was proposed to support the test of elements within the boards. It is a large serial shift register that uses the TDI pin as an input and the TDO pin as an output. Even though it performs the board level test perfectly, there is a problems of running system level test when the boards are equipped to the system. To test real time operation signal on test pin, output speed of serial shift register chain must be above double clock speed of shift register. In this paper, we designed a runtime test architecture and a runtime test procedure under running system environments to capture runtime signal at system clock rate. The suggested runtime test architecture are simulated by Altera Max+Plus 10.0. through the runtime test procedure. The simulation results show that operations of the suggested runtime test architecture are very accurate.

KEYWORDS

Run-time test, IEEE 1149.1, Boundary Scan Register, Test Access Port

Citation status

* References for papers published after 2023 are currently being built.

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Journal of The Korea Society of Computer and Information 2023 KCI Impact Factor : 0.65