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CORDIC using Heterogeneous Adders for Better Delay, Area and Power Trade-offs

  • Journal of The Korea Society of Computer and Information
  • Abbr : JKSCI
  • 2010, 15(2), pp.9-17
  • Publisher : The Korean Society Of Computer And Information
  • Research Area : Engineering > Computer Science

이병석 1 이정근 2 Jeong-A Lee 1

1조선대학교
2한림대학교

Accredited

ABSTRACT

High performance is required with small size and low power in the mobile embedded system. A CORDIC algorithm can compute transcendental functions effectively with only small adders and shifters and is suitable one for the mobile embedded system. However CORDIC unit has performance degradation according due to iterative inter-rotations. Adder design is an important design unit to be optimized for a high performance and low power CORDIC unit. It is necessary to explore the design space of a CORDIC unit considering trade-offs of an adder unit while satisfying delay, area and power constraints. In this paper, we suggest a CORDIC architecture employing a heterogeneous adder and an optimization methodology for producing better optimal tradeoff points of CORDIC designs.

Citation status

* References for papers published after 2023 are currently being built.

This paper was written with support from the National Research Foundation of Korea.