nalysis on the Performance and Temperature of the 3D Quad-core Processor according to Cache Organization (캐쉬 구성에 따른 3차원 쿼드코어 프로세서의 성능 및 온도 분석)

손동오; 안진우; 최홍준; Jong Myon Kim (김종면); Cheol Hong Kim (김철홍)

nalysis on the Performance and Temperature of the 3D Quad-core Processor according to Cache Organization

Journal of The Korea Society of Computer and Information
Abbr : JKSCI
2012, 17(6), pp.1-11
Publisher : The Korean Society Of Computer And Information
Research Area : Engineering > Computer Science

손동오 ¹, 안진우 ¹, 최홍준 ¹, Jong Myon Kim ², Cheol Hong Kim ¹

¹전남대학교
²울산대학교

Accredited

ABSTRACT

As the process technology scales down, multi-core processors cause serious problems such as increased interconnection delay, high power consumption and thermal problems. To solve the problems in 2D multi-core processors, researchers have focused on the 3D multi-core processor architecture. Compared to the 2D multi-core processor, the 3D multi-core processor decreases interconnection delay by reducing wire length significantly, since each core on different layers is connected using vertical through-silicon via(TSV). However, the power density in the 3D multi-core processor is increased dramatically compared to that in the 2D multi-core processor, because multiple cores are stacked vertically. Unfortunately, increased power density causes thermal problems, resulting in high cooling cost, negative impact on the reliability. Therefore, temperature should be considered together with performance in designing 3D multi-core processors. In this work, we analyze the temperature of the cache in quad-core processors varying cache organization. Then, we propose the low-temperature cache organization to overcome the thermal problems. Our evaluation shows that peak temperature of the instruction cache is lower than threshold. The peak temperature of the data cache is higher than threshold when the cache is composed of many ways. According to the results, our proposed cache organization not only efficiently reduces the peak temperature but also reduces the performance degradation for 3D quad-core processors.

KEYWORDS

Quad-core processor, 3D integrated circuits, Temperature, Cache memory, Mapping method

Citation status

* References for papers published after 2023 are currently being built.

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This paper was written with support from the National Research Foundation of Korea.

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Journal Central

Journal of The Korea Society of Computer and Information 2023 KCI Impact Factor : 0.65