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Instruction Flow based Early Way Determination Technique for Low-power L1 Instruction Cache

  • Journal of The Korea Society of Computer and Information
  • Abbr : JKSCI
  • 2016, 21(9), pp.1-9
  • Publisher : The Korean Society Of Computer And Information
  • Research Area : Engineering > Computer Science

Gwang Bok Kim 1 Jong Myon Kim 2 Cheol Hong Kim 1

1전남대학교
2울산대학교

Accredited

ABSTRACT

Recent embedded processors employ set-associative L1 instruction cache to improve the performance. The energy consumption in the set-associative L1 instruction cache accounts for considerable portion in the embedded processor. When an instruction is required from the processor, all ways in the set-associative instruction cache are accessed in parallel. In this paper, we propose the technique to reduce the energy consumption in the set-associative L1 instruction cache effectively by accessing only one way. Gshare branch predictor is employed to predict the instruction flow and determine the way to fetch the instruction. When the branch prediction is untaken, next instruction in a sequential order can be fetched from the instruction cache by accessing only one way. According to our simulations with SPEC2006 benchmarks, the proposed technique requires negligible hardware overhead and shows 20% energy reduction on average in 4-way L1 instruction cache.

Citation status

* References for papers published after 2022 are currently being built.

This paper was written with support from the National Research Foundation of Korea.