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Verification for the design limit margin of the power device using the HALT reliability test

  • Journal of The Korea Society of Computer and Information
  • Abbr : JKSCI
  • 2018, 23(11), pp.67-74
  • DOI : 10.9708/jksci.2018.23.11.067
  • Publisher : The Korean Society Of Computer And Information
  • Research Area : Engineering > Computer Science
  • Received : September 21, 2018
  • Accepted : October 22, 2018
  • Published : November 30, 2018

Yushin Chang 1

1한화시스템

Accredited

ABSTRACT

The verification for the design limit margin of the power device for the information communication and surveillance systems using HALT(Highly Accelerated Life Test) reliability test is described. The HALT reliability test performs with a step stress method which change condition until the marginal step in a design and development phase. The HALT test methods are the low temperature(cold) step stress test, the high temperature(hot) step stress test, the thermal shock cyclic stess test, and the high temperature destruct limit(hot DL) step stress test. The power device is checked the operating performance during the test. In this paper, the HALT was performed to find out the design limit margin of the power device.

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