Energy-aware Instruction Cache Design using Backward Branch Information for Embedded Processors (임베디드 시스템에서 후방 분기 명령어 정보를 이용한 저전력 명령어 캐쉬 설계 기법)

양나라; Jong Myon Kim (김종면); 김철홍

Energy-aware Instruction Cache Design using Backward Branch Information for Embedded Processors

Journal of The Korea Society of Computer and Information
Abbr : JKSCI
2008, 13(6), pp.33-40
Publisher : The Korean Society Of Computer And Information
Research Area : Engineering > Computer Science

양나라 ¹, Jong Myon Kim ², 김철홍 ¹

¹전남대학교
²울산대학교

Accredited

ABSTRACT

Energy efficiency should be considered together with performance when designing embedded processors. This paper proposes a new energy-aware instruction cache design using backward branch information to reduce the energy consumption in an embedded processor, since instruction caches consume a significant fraction of the on-chip energy. Proposed instruction cache is composed of two caches: a large main instruction cache and a small loop instruction cache. Proposed technique enables the selective access between the main instruction cache and the loop instruction cache to reduce the number of accesses to the main instruction cache, leading to good energy efficiency. Analysis results show that the proposed instruction cache reduces the energy consumption by 20% on the average, compared to the traditional instruction cache.

KEYWORDS

Embedded System, Processor Architecture, Low-power System, Instruction Cache

Citation status

* References for papers published after 2023 are currently being built.

[confproc] K. Ghose / 1999 / Reducing Power in Superscalar Processor Caches using Subbanking, Multiple Line Buffers and Bit-line Segmentation / In Proceedings of International Symposium on Low Power Electronics and Design : 70~75

[journal] M. B. Kamble / 1997 / Analytical Energy Dissipation Models for Low-Power Caches / In Proceedings of International Symposium on Low Power Electronics and Design : 143~148

[confproc] A. Ma / 2001 / Way Memorization to Reduce Fetch Energy in Instruction Caches / In Workshop on Complexity-Effective Design, 28th ISCA

[confproc] E. Witchel / 2001 / The Span Cache: Software Controlled Tag Checks and Cache Line Size / In Workshop on Complexity-Effective Design, 28th ISCA

[confproc] J. Montanaro / 1996 / A 160 Mhz, 32b, 0.5W CMOS RISC Microprocessor / In Proceedings of International Solid-State Circuits Conference : 214~229

[confproc] S. Segars / 2001 / Low Power Design Techniques for Microprocessors / In Proceedings of International Solid-State Circuits Conference

[confproc] J. Kin / 1997 / The Filter Cache: An Energy Efficient Memory Structure / In Proceedings of International Symposium on Microarchitecture : 184~193

[confproc] K. Vivekanandarajah / 2004 / Decode Filter Cache for Energy Efficient Instruction Cache Hierarchy in Superscalar architectures / In Proceedings of 2004 Conference on Asia South Pacific Design Automation : 373~379

[confproc] R. Giorgi / 2007 / Reducing Leakage in Power-saving Capable Caches for Embedded Systems by Using a Filter Cache / In Proceedings of the 2007 Workshop on Memory Performance: Dealing with Applications, Systems, and Architecture : 97~104

[confproc] N. Bellas / 1999 / Using Dynamic Cache Management Techniques to Reduce Energy in a High-performance Processor / In Proceedings of International Symposium on Low Power Electronics and Design : 64~69

[confproc] David H. Albonesi / 1999 / Selective Cache Ways: On Demand Cache Resource Allocation / In Proceedings of International Symposium on Microarchitecture : 70~75

[journal] M. Powell / 2001 / Reducing Set-Associative Cache Energy via Way-Prediction and Selective Direct-Mapping / In Proceedings of International Symposium on Microarchitecture : 54~65

[journal] C. H. Kim / 2006 / PP-cache: A Partitioned Power-aware Instruction Cache Architecture / Microprocessors and Microsystems 30(5) : 268~279

[book] D. Burger / 1997 / Evaluating Future Microprocessors: the Simplescalar tool set / Technical Report TR-1308, Univ. of Wisconsin-Madison Computer Sciences Dept

[book] P. Shivakumar / 2001 / Cacti 3.0: An Integrated Cache Timing, Power, and Area Model / Technical Report TRWRL-2001-2, Univ. of Wisconsin-Madison Computer Sciences Dept

[web] / ARM.ARM1136J(F)-S / http://www.arm.com/products/CPUs/ARM1136JF-S.html.

[web] / SPEC.SPEC CPU2000 Benchmarks / http://www.specbench.org

KJCKorea
Journal Central

Journal of The Korea Society of Computer and Information 2023 KCI Impact Factor : 0.65