Bypassing Scheme for Inclusive Last Level Caches (포괄적 마지막 수준 캐시를 위한 바이패싱 기법)

Lee Sang Jeong (이상정); Youngil Cho (조영일)

Bypassing Scheme for Inclusive Last Level Caches

Journal of Knowledge Information Technology and Systems
Abbr : JKITS
2016, 11(2), pp.155-162
Publisher : Korea Knowledge Information Technology Society
Research Area : Interdisciplinary Studies > Interdisciplinary Research
Published : April 30, 2016

Lee Sang Jeong ¹, Youngil Cho ²

¹순천향대학교
²수원대학교

Accredited

ABSTRACT

The design of an effective last level cache(LLC) continues to be an important issue in processor‘s performance. Recent works on high performance caches have shown that cache bypassing is an effective technique to enhance the performance of last level caches. However, commonly used inclusive cache hierarchy cannot benefit from this technique because bypassing inherently breaks the inclusion property. This paper presents a solution to enabling cache bypassing for inclusive caches. It introduces a bypass buffer to an LLC. Bypassed cache lines skip the LLC while their entries are allocated into the bypass buffer. And it is a simple, low-hardware overhead, yet effective, cache bypassing scheme that dynamically chooses which blocks to insert into the LLC and which blocks to bypass it based on past access/bypass patterns on a miss. Our proposed scheme is evaluated using a detailed simulation environment where its effectiveness, performance-improvement capabilities, and robustness are demonstrated. We present experimental results showing IPC(Instruction Per Cycle) comparison of the proposed scheme and OBM(Optimal Bypass Monitor) against LRU for SPEC CPU2006 benchmarks. The result show that the proposed scheme and OBM can improve IPC by an average of 18% and 14%, respectively. And the proposed scheme reduces the miss rate by 16% compared to LRU.

KEYWORDS

LLC(last-level cache), Cache bypassing, Inclusive caches, Exclusive caches, Bypass buffers

Citation status

* References for papers published after 2023 are currently being built.

[confproc] X. Chen. / 2014 / Adaptive cache bypass and insertion for many-core accelerators / MICRO-2014

[confproc] N. Duong. / 2012 / Improving cache management policies using dynamic reuse distances / MICRO-2012 : 389~400

[confproc] M. Gebhart. / 2011 / Energy-efficient mechanisms for managing thread context in throughput processors / ISCA-2011 : 235~246

[journal] 이상정 / 2015 / A Cache Replacement Policy for Improving the Performance of Last Level Cache in Processors / 한국지식정보기술학회 논문지 / 한국지식정보기술학회 10(2) : 145~152

[confproc] A. Jaleel. / 2010 / Achieving non-inclusive cache performance with inclusive caches -temporal locality aware (TLA) cache management policies / MICRO-2010 : 151~162

[confproc] A. Jaleel. / 2010 / High performance cache replacement using re-reference interval prediction (RRIP) / ISCA-2010 : 60~71

[confproc] J. Gaur. / 2011 / Bypass and insertion algorithms for exclusive last-level caches / ISCA-2011 : 81~92

[confproc] S. Gupta. / 2013 / Adaptive cache bypassing for inclusive last level caches / IPDPS-2013 : 1243~1253

[confproc] L. Li. / 2013 / Optimal bypass monitor for high performance last-level caches / PACT-2013 : 315~324

[confproc] M. Chaudhuri / 2013 / Introducing hierarchy-awareness in replacement and bypass algorithms for last-level caches / PACT-2013 : 293~304

[journal] M. Kharbutli. / 2008 / Counter-based cache replacement and bypassing algorithms / IEEE Trans. on Computers 57(4) : 433~447

[confproc] H. Dybdahl. / 2006 / Enhancing last-level cache performance by block bypassing and early miss determination / ACSAC-2006 : 52~66

[confproc] C. Li. / 2015 / Locality-driven dynamic GPU cache bypassing / ICS-2015 : 67~77

[confproc] V. Krishnan. / 1998 / A direct-execution framework for fast and accurate simulation of superscalar processors / PACT 1998 : 286~293

[web] / 2015 / SimPoint home page / http://cseweb.ucsd.edu/~calder/simpoint/

KJCKorea
Journal Central

Journal of Knowledge Information Technology and Systems 2023 KCI Impact Factor : 0.89