@article{ART002359255},
author={Cho Yong Suk and Shin，Yong-Dal},
title={Design of Low-Complexity Decoder for Triple Error Correcting BCH Codes},
journal={Journal of Knowledge Information Technology and Systems},
issn={1975-7700},
year={2018},
volume={13},
number={3},
pages={373-379},
doi={10.34163/jkits.2018.13.3.008}
TY - JOUR
AU - Cho Yong Suk
AU - Shin，Yong-Dal
TI - Design of Low-Complexity Decoder for Triple Error Correcting BCH Codes
JO - Journal of Knowledge Information Technology and Systems
PY - 2018
VL - 13
IS - 3
PB - Korea Knowledge Information Technology Society
SP - 373
EP - 379
SN - 1975-7700
AB - The Bose-Chaudhuri-Hocquenghem (BCH) codes are a class of powerful multiple-error-correcting cyclic codes. Due to its powerful error-correction performance and reasonable hardware costs, the binary BCH codes have been widely used in data communications and storage systems for error control. In this paper, a design method of low-complexity decoder for triple error correcting binary BCH codes is presented, which is modified Peterson's direct solution method. In this method, all division operations over finite field GF(2^m)are eliminated from the computations of the error locator polynomial. BCH codes are defined over finite field GF(2^m) and all arithmetic operations are performed over this fields. Inversion in a finite field is time consuming and requires relatively complex circuitry. In conventional decoding algorithm of BCH codes are required finite field inversion. In this paper, inversionless decoder for triple error correcting BCH codes is proposed. The decoder comprises a syndrome computation circuit, a error locator polynomial computation circuit and a error location searching circuit, which can be implemented by linear feedback shift registers and logical gates. The attractive feature of this decoder is its remarkable simplicity from the point of view of hardware implementation. Futhermore, the proposed decoder has very simple control circuit and short decoding delay. Therefore this decoder can be implemented by simple hardware and also save buffer memory which stores received sequence.
KW - Error correction codes;BCH codes;Peterson’s algorithm;Galois fields;Finite fields inversion
DO - 10.34163/jkits.2018.13.3.008
ER -
Cho Yong Suk and Shin，Yong-Dal. (2018). Design of Low-Complexity Decoder for Triple Error Correcting BCH Codes. Journal of Knowledge Information Technology and Systems, 13(3), 373-379.
Cho Yong Suk and Shin，Yong-Dal. 2018, "Design of Low-Complexity Decoder for Triple Error Correcting BCH Codes", Journal of Knowledge Information Technology and Systems, vol.13, no.3 pp.373-379. Available from: doi:10.34163/jkits.2018.13.3.008
Cho Yong Suk, Shin，Yong-Dal "Design of Low-Complexity Decoder for Triple Error Correcting BCH Codes" Journal of Knowledge Information Technology and Systems 13.3 pp.373-379 (2018) : 373.
Cho Yong Suk, Shin，Yong-Dal. Design of Low-Complexity Decoder for Triple Error Correcting BCH Codes. 2018; 13(3), 373-379. Available from: doi:10.34163/jkits.2018.13.3.008
Cho Yong Suk and Shin，Yong-Dal. "Design of Low-Complexity Decoder for Triple Error Correcting BCH Codes" Journal of Knowledge Information Technology and Systems 13, no.3 (2018) : 373-379.doi: 10.34163/jkits.2018.13.3.008
Cho Yong Suk; Shin，Yong-Dal. Design of Low-Complexity Decoder for Triple Error Correcting BCH Codes. Journal of Knowledge Information Technology and Systems, 13(3), 373-379. doi: 10.34163/jkits.2018.13.3.008
Cho Yong Suk; Shin，Yong-Dal. Design of Low-Complexity Decoder for Triple Error Correcting BCH Codes. Journal of Knowledge Information Technology and Systems. 2018; 13(3) 373-379. doi: 10.34163/jkits.2018.13.3.008
Cho Yong Suk, Shin，Yong-Dal. Design of Low-Complexity Decoder for Triple Error Correcting BCH Codes. 2018; 13(3), 373-379. Available from: doi:10.34163/jkits.2018.13.3.008
Cho Yong Suk and Shin，Yong-Dal. "Design of Low-Complexity Decoder for Triple Error Correcting BCH Codes" Journal of Knowledge Information Technology and Systems 13, no.3 (2018) : 373-379.doi: 10.34163/jkits.2018.13.3.008
