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A New Bit-Serial/Digit-Parallel Multiplier in GF(2^m) UsingNormal Basis

  • Journal of Knowledge Information Technology and Systems
  • Abbr : JKITS
  • 2019, 14(2), pp.203-210
  • DOI : 10.34163/jkits.2019.14.2.010
  • Publisher : Korea Knowledge Information Technology Society
  • Research Area : Interdisciplinary Studies > Interdisciplinary Research
  • Received : March 18, 2019
  • Accepted : April 12, 2019
  • Published : April 30, 2019

Cho Yong Suk 1,  Shin，Yong-Dal 1

1유원(U1)대학교

Accredited

ABSTRACT

The Arithmetic operations over GF(2^m) have been extensively used in public-key cryptography schemes and error correcting codes. Among the arithmetic operations over GF(2^m), the efficient implementation of field multiplication is of upmost importance, as field operations of greater complexity (e.g., exponentiation and division) can be performed by the consecutive use of field multiplication. Choosing the basis by which field elements are represented plays an important role in the efficient implementation of finite field multiplications. There are three popular and applicable basis, namely, polynomial basis (PB), normal basis (NB), and dual basis. Hardware implementations of finite field multiplier using normal basis are advantageous due to the fact that the squaring operation can be performed by only one-bit cyclic shift at almost no cost. In this paper, a new bit-serial/digit-parallel multiplier using normal basis of GF(2^m) is presented. The main idea of the proposed multiplier is to use this feature of normal basis. In the proposed multiplier, the bits of an operand are grouped into several digits with bits and each digit is implemented simultaneously by bit-serial multiplier. Therefore, the proposed multiplier takes clock cycles, , to finish one multiplication operation in GF(2^m). The value of can be selected by designer to set the trade off between area and speed according to the application. The proposed multiplier has lower area complexity than bit-parallel multiplier and is faster than bit-serial ones. In addition, the proposed multiplier has higher regular architecture compared to other similar proposals and therefore, well-suited for VLSI implementation and can be easily applied as a basic component for computing complex operations over finite field, such as exponentiation and division operation.

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